CY7C4122KV13/CY7C4142KV13 144-Mbit QDR-IV XP SRAM e 144-Mbit QDR-IV XP SRAM Features Configurations CY7C4122KV13 8M 18 144-Mbit density (8M 18, 4M 36) 1 CY7C4142KV13 4M 36 Total Random Transaction Rate of 2132 MT/s Functional Description Maximum operating frequency of 1066 MHz Read latency of 8.0 clock cycles and write latency of 5.0 clock The QDR-IV XP (Xtreme Performance) SRAM is a cycles high-performance memory device optimized to maximize the number of random transactions per second by the use of two Eight-bank architecture enables one access per bank per cycle independent bidirectional data ports. Two-word burst on all accesses These ports are equipped with DDR interfaces and designated as port A and port B respectively. Accesses to these two data Dual independent bidirectional data ports ports are concurrent and independent of each other. Access to Double data rate (DDR) data ports each port is through a common address bus running at DDR. The Supports concurrent read/write transactions on both ports control signals are running at SDR and determine if a read or write should be performed. Single address port used to control both data ports DDR address signaling There are three types of differential clocks: Single data rate (SDR) control signaling (CK, CK ) for address and command clocking High-speed transceiver logic (HSTL) and stub series termi- (DKA, DKA , DKB, DKB ) for data input clocking nated logic (SSTL) compatible signaling (JESD8-16A (QKA, QKA , QKB, QKB ) for data output clocking compliant) I/O V = 1.2 V 50 mV or 1.25 V 50 mV Addresses for port A are latched on the rising edge of the input DDQ clock (CK), and addresses for port B are latched on the falling Pseudo open drain (POD) signaling (JESD8-24 compliant) edge of the input clock (CK). I/O V = 1.1 V 50 mV or 1.2 V 50 mV DDQ This QDR-IV XP SRAM is internally partitioned into eight internal Core voltage banks. Each bank can be accessed once for every clock cycle, V = 1.3 V 40 mV enabling the SRAM to operate at high frequencies. DD The QDR-IV XP SRAM device is offered in a two-word burst On-die termination (ODT) option and is available in 18 and 36 bus width configurations. Programmable for clock, address/command, and data inputs For an 18 bus-width configuration, there are 22 address bits, Internal self-calibration of output impedance through ZQ pin and for an 36 bus width configuration, there are 21 address bits Bus inversion to reduce switching noise and power respectively. Programmable on/off for address and data An on-chip ECC circuitry detects and corrects all single-bit memory errors including those induced by soft error events, such Address bus parity error protection as cosmic rays and alpha particles. The resulting SER of these Training sequence for per-bit deskew devices is expected to be less than 0.01FITs/Mb, a four-order-of-magnitude improvement over previous generation On-chip error correction code (ECC) to reduce soft error rate SRAMs. (SER) For a complete list of related resources, click here. JTAG 1149.1 test access port (JESD8-26 compliant) 1.3-V LVCMOS signaling Available in 361-ball FCBGA Pb-free package (21 21 mm) Selection Guide QDR-IV QDR-IV Description Unit 2132 (MT/s) 1866 (MT/s) Maximum operating frequency 1066 933 MHz Maximum operating current 18 4100 3400 mA 36 4500 4000 Note 1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured in million transactions per second. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-68255 Rev. *Q Revised April 21, 2017CY7C4122KV13/CY7C4142KV13 Logic Block Diagram CY7C4122KV13 Document Number: 001-68255 Rev. *Q Page 2 of 46