54
CY7C451
CY7C453
CY7C454
512x9, 2Kx9, and 4Kx9 Cascadable
Clocked FIFOs with Programmable
and write interfaces. Both FIFOs are 9 bits wide. The
Features
CY7C451 has a 512-word by 9-bit memory array, the
High-speed, low-power, first-in first-out (FIFO) CY7C453 has a 2048-word by 9-bit memory array, and the
memories
CY7C454 has a 4096-word by 9-bit memory array. Devices
can be cascaded to increase FIFO depth. Programmable fea-
512 x 9 (CY7C451)
tures include Almost Full/Empty flags and generation/checking
2,048 x 9 (CY7C453)
of parity. These FIFOs provide solutions for a wide variety of data
4,096 x 9 (CY7C454)
buffering needs, including high-speed data acquisition, multiproces-
0.65 micron CMOS for optimum speed/power
sor interfaces, and communications buffering.
High-speed 83-MHz operation (12 ns read/write cycle
Both FIFOs have 9-bit input and output ports that are con-
time)
trolled by separate clock and enable signals. The input port is
Low power I =70 mA
CC
controlled by a free-running clock (CKW) and a write enable
Fully asynchronous and simultaneous read and write
pin (ENW). When ENW is asserted, data is written into the FIFO on
operation
the rising edge of the CKW signal. While ENW is held active, data is
Empty, Full, Half Full, and programmable Almost Empty
continually written into the FIFO on each CKW cycle. The output port
and Almost Full status flags
is controlled in a similar manner by a free-running read clock (CKR)
TTL compatible and a read enable pin (ENR). The read (CKR) and write (CKW)
clocks may be tied together for single-clock operation or the two
Retransmit function
clocks may be run independently for asynchronous read/write appli-
Parity generation/checking
cations. Clock frequencies up to 83.3 MHz are achievable in the stan-
Output Enable (OE ) pins
dalone configuration, and up to 83.3 MHz is achievable when FIFOs
Independent read and write enable pins
are cascaded for depth expansion.
Center power and ground pins for reduced noise
Depth expansion is possible using the cascade input (XI) and
Supports free-running 50% duty cycle clock inputs
cascade output (XO). The XO signal is connected to the XI of the next
Width Expansion Capability device, and the XO of the last device should be connected to the XI
of the first device. In standalone mode, the input (XI) pin is simply tied
Depth Expansion Capability
to V .
SS
Available in PLCC packages
In the standalone and width expansion configurations, a LOW
Functional Description
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (ENR) and the write enable (ENW) must
The CY7C451, CY7C453, and CY7C454 are high-speed,
both be HIGH during the retransmit, and then ENR is used to
low-power, first-in first-out (FIFO) memories with clocked read
access the data.
D0 8
Logic Block Diagram
Pin Configurations
INPUT
REGISTER
PLCC/LCC
Top View
CKW ENW
D D D D D D D
0 1 2 3 4 5 6
FLAG/PARITY
4 32 32 31 30
1
PARITY
PROGRAM
XI D
WRITE 29 7
REGISTER
5
D
CONTROL ENW
8
28
6
CKW FL/RT
27
7
V 7C451
CC 26 MR
HF
8
FLAG V
7C453
SS 25 V
SS
E/F 9
LOGIC
7C454
HF
CKR
24
PAFE/XO 10
RAM
E/F ENR
23
ARRAY 11
512x9 OE
PAFE/XO 22
12
2048x 9 Q
READ
WRITE Q 21 8 /PG/PE
0 13
4096x9
POINTER
POINTER
14 15 16 17 1819 20
Q Q Q Q Q Q Q
1 2 3 4 5 6 7
MR
C451-2
RESET
LOGIC
FL/RT
TRISTATE
READ
EXPANSION
OUTPUT REGISTER
XI
CONTROL
LOGIC
OE
RETRANSMIT
LOGIC Q Q /PG/PE
07, 8 CKR ENR
C451-1
Cypress Semiconductor Corporation 3901NorthFirstStreet SanJose CA 95134 408-943-2600
Document #: 38-06033 Rev. *A Revised December 27, 2002
CY7C451
CY7C453
CY7C454
entering or exiting the Empty and Almost Empty states, the
Functional Description (continued)
flags are updated exclusively by the CKR. The flags denoting
The CY7C451, CY7C453, and CY7C454 provide three status pins Half Full, Almost Full, and Full states are updated exclusively
to the user. These pins are decoded to determine one of six states: by CKW. The synchronous flag architecture guarantees that
Empty, Almost Empty, Less than or Equal to Half Full, Greater than the flags maintain their status for some minimum time.
Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full
The CY7C451, CY7C453, and the CY7C454 use center power
flag (PAFE) and XO functions share the same pin. The Almost Emp-
and ground for reduced noise. Both configurations are fabri-
ty/Full flag is valid in the standalone and width expansion con-
cated using an advanced RAM 2.8 technology. Input ESD
figurations. In the depth expansion, this pin provides the
protection is greater than 2001V, and latch-up is prevented
expansion out (XO) information that is used to signal the
by the use of reliable layout techniques and guard rings.
next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to
either the read clock (CKR) or the write clock (CKW). When
Selection Guide
7C451-12 7C451-14 7C451-20 7C451-30
7C453-12 7C453-14 7C453-20 7C453-30
7C454-12 7C454-14 7C454-20 7C454-30
Maximum Frequency (MHz) 83.3 71.4 50 33.3
Maximum Cascadable Frequency 83.3 71.4 50 33.3
Maximum Access Time (ns) 9 10 15 20
Minimum Cycle Time (ns) 12 14 20 30
Minimum Clock HIGH Time (ns) 5 6.5 9 12
Minimum Clock LOW Time (ns) 5 6.5 9 12
Minimum Data or Enable Set-Up (ns) 4 5 6 7
Minimum Data or Enable Hold (ns) 0 0 0 0
Maximum Flag Delay (ns) 9 10 15 20
Maximum Current (mA) Commercial 140 140 120 100
Military/Industrial 150 150 130 110
Selection Guide (continued)
CY7C451 CY7C453 CY7C454
Density 512 x 9 2,048 x 9 4,096 x 9
OE, Depth Cascadable Yes Yes Yes
Package 32-Pin PLCC 32-Pin PLCC 32-Pin PLCC
[1]
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-Up Current.................................................... > 200 mA
Storage Temperature ....................................65C to +150C
Ambient Temperature with
Operating Range
Power Applied.................................................55C to +125C
Ambient
Supply Voltage to Ground Potential .................0.5V to +7.0V
Range Temperature V
CC
DC Voltage Applied to Outputs
Commercial 0C to +70C 5V 10%
in High Z State .....................................................0.5V to +7.0V
Industrial 40C to +85C 5V 10%
DC Input Voltage .................................................3.0V to +7.0V
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during
power-up.
Document #: 38-06033 Rev. *A Page 2 of 24