CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description True dual port memory enables simultaneous access the The FullFlex dual port SRAM families consist of 2-Mbit, 9-Mbit, shared array from each port 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports Synchronous pipelined operation with single data rate (SDR) are provided, enabling simultaneous access to the array. operation on each port Simultaneous access to a location triggers deterministic access SDR interface at 200 MHz control. For FullFlex72 these ports operate independently with Up to 28.8 Gb/s bandwidth (200 MHz 72-bit 2 ports) 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in Selectable pipelined or flow-through mode pipelined or flow through mode. 1.5 V or 1.8 V core power supply The advanced features include the following: Commercial and Industrial temperature Built in deterministic access control to manage address collisions during simultaneous access to the same memory IEEE 1149.1 JTAG boundary scan location Available in 484-ball PBGA ( 72) and 256-ball FBGA ( 36 Variable impedance matching (VIM) to improve data and 18) packages transmission by matching the output driver impedance to the FullFlex72 family line impedance 36-Mbit: 512 K 72 (CYD36S72V18) Echo clocks to improve data transfer 18-Mbit: 256 K 72 (CYD18S72V18) To reduce the static power consumption, chip enables power 9-Mbit: 128 K 72 (CYD09S72V18) down the internal circuitry. The number of latency cycles before FullFlex36 family a change in CE or CE enables or disables the databus 0 1 36-Mbit: 1 M 36 (CYD36S36V18) matches the number of cycles of read latency selected for the 18-Mbit: 512 K 36 (CYD18S36V18) device. For a valid write or read to occur, activate both chip enable inputs on a port. 9-Mbit: 256 K 36 (CYD09S36V18) 2-Mbit: 64 K 36 (CYD02S36V18) Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial FullFlex18 family address, the counter increments the address internally. 36-Mbit: 2 M 18 (CYD36S18V18) Additional device features include a mask register and a mirror 18-Mbit: 1 M 18 (CYD18S18V18) register to control counter increments and wrap around. The 9-Mbit: 512 K 18 (CYD09S18V18) counter interrupt (CNTINT) flags notify the host that the counter Built in deterministic access control to manage address reaches maximum count value on the next clock cycle. The host collisions reads the burst counter internal address, mask register address, Deterministic flag output upon collision detection and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the Collision detection on back-to-back clock cycles retransmit functionality. Mailbox interrupt flags are used for First busy address readback message passing, and JTAG boundary scan and asynchronous Advanced features for improved high speed data transfer and Master Reset (MRST) are also available. The Logic Block flexibility Diagram on page 2 shows these features. Variable impedance matching (VIM) The FullFlex72 is offered in a 484-ball plastic BGA package. The Echo clocks FullFlex36 and FullFlex18 are available in 256-ball fine pitch Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V), BGA package except the 36-Mbit devices which are offered in 1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port 484-ball plastic BGA package. Burst counters for sequential memory access For a complete list of related documentation, click here. Mailbox with interrupt flags for message passing Dual chip enables for easy depth expansion Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06082 Rev. *Q Revised November 27, 2014CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Logic Block Diagram 1, 2, 3 The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: FTSEL FTSEL L R CQEN CQEN L R CONFIG Block CONFIG Block PORTSTD 1:0 L PORTSTD 1:0 R DQ 71:0 DQ 71:0 R L BE 7:0 BE 7:0 R L CE0 CE0 R L IO IO CE1 CE1 L R OE OE Control Control R L R/W R/W R L CQ1 L CQ1 R CQ1 L CQ1 R CQ0 L CQ0 R CQ0 L CQ0 R Dual Port Array BUSY Collision Detection Logic BUSY L R A 20:0 A 20:0 L R CNT/MSK CNT/MSK L R ADS ADS L R CNTEN CNTEN R L Address & Address & CNTRST CNTRST L R Counter Logic RET Counter Logic RET L R CNTINT L CNTINT R C C L R WRP L WRP R TRST Mailboxes TMS INT INT L R TDI JTAG TDO TCK ZQ0 ZQ0 R L ZQ1 ZQ1 R L RESET MRST LOGIC READY READY L R LowSPD LowSPD L R Notes 1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. 2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. Document Number: 38-06082 Rev. *Q Page 2 of 53