S25FL032P 32-Mbit 3.0 V Flash Memory This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede S25FL032P. These are the factory-recommended migration paths. Refer to the S25FL-L Family datasheets for specifications and ordering information. Distinctive Characteristics Common Flash Interface (CFI) compliant: allows host system Architectural Advantages to identify and accommodate multiple flash devices Single power supply operation Process technology Full voltage range: 2.7 V to 3.6 V read and write operations Manufactured on 0.09 m MirrorBit process technology Memory architecture Package option Uniform 64-KB sectors Industry Standard Pinouts Top or bottom parameter block (two 64-KB sectors (top 8-pin SO package (208 mils) or bottom) broken down into 16 4-KB sub-sectors each) 16-pin SO package (300 mils) 256-byte page size 8-contact USON package (5 6 mm) Backward compatible with the S25FL032A device 8-contact WSON package (6 8 mm) Program 24-ball BGA 6 8 mm package, 5 5 pin configuration Page Program (up to 256 bytes) in 1.5 ms (typical) 24-ball BGA 6 8 mm package, 6 4 pin configuration Program operations are on a page by page basis Accelerated programming mode via 9-V W /ACC pin Performance Characteristics Quad Page Programming Speed Erase Normal READ (Serial): 40-MHz clock rate Bulk erase function FAST READ (Serial): 104-MHz clock rate (maximum) Sector erase (SE) command (D8h) for 64-KB sectors DUAL I/O FAST READ: 80-MHz clock rate or Sub-sector erase (P4E) command (20h) for 4-KB sectors 20 MB/s effective data rate Sub-sector erase (P8E) command (40h) for 8-KB sectors QUAD I/O FAST READ: 80 MHz clock rate or Cycling endurance 40 MB/s effective data rate 100,000 cycles per sector typical Power saving standby mode Data retention Standby Mode 80 A (typical) 20 years typical Deep Power-Down Mode 3 A (typical) Device ID JEDEC standard two-byte electronic signature Memory Protection Features RES command one-byte electronic signature for backward Memory protection compatibility W /ACC pin works in conjunction with Status Register Bits One time programmable (OTP) area for permanent, secure to protect specified memory areas identification can be programmed and locked at the factory Status Register Block Protection bits (BP2, BP1, BP0) in or by the customer status register configure parts of memory as read-only Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00650 Rev. *L Revised May 19, 2017 Not Recommended for New DesignS25FL032P General Description The S25FL032P is a 3.0 V (2.7 V to 3.6 V), single-power-supply Flash memory device. The device consists of 64 uniform 64-KB sectors with the two (top or bottom) 64-KB sectors further split up into thirty-two 4-KB sub sectors. The S25FL032P device is fully backward compatible with the S25FL032A device. The device accepts data written to Serial Input (SI) and outputs data on Serial Output (SO). The devices are designed to be programmed in-system with the standard system 3.0-V V supply. CC The S25FL032P device adds the following high-performance features using five new instructions: Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz Quad Output Read using SI, SO, W /ACC, and HOLD pins as output pins at a clock rate of up to 80 MHz Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz Quad I/O High Performance Read using SI, SO, W /ACC, and HOLD pins as input and output pins at a clock rate of up to 80 MHz Quad Page Programming using SI, SO, W /ACC, and HOLD pins as input pins to program data at a clock rate of up to 80 MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0-V power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device requires a high voltage supply to the W /ACC pin to enable the Accelerated Programming mode. The S25FL032P device also offers a One-Time Programmable area (OTP) of up to 128 bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions. Document Number: 002-00650 Rev. *L Page 2 of 60 Not Recommended for New Design