Product Information

S29AL032D90WEI049

S29AL032D90WEI049 electronic component of Infineon

Datasheet
NOR Flash Parallel 3V/3.3V 32M-bit 4M x 8/2M x 16 90ns 48-Pin Wafer Jar

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 7.014 ea
Line Total: USD 35.07

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 5
Multiples : 1
5 : USD 7.014
25 : USD 6.2861
100 : USD 3.9834
500 : USD 3.4144
1000 : USD 2.9909
2500 : USD 2.3954
5000 : USD 2.3027
10000 : USD 2.2101
25000 : USD 2.1307

     
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S29AL032D Known Good Die 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory Supplement General Description The S29AL032D in Known Good Die (KGD) form is 32 Mbit, 3.0 volt-only Flash memory. Spansion defines KGD as standard product in die form, tested for functionality and speed. Spansion KGD products have the same reliability and quality as Spansion products in packaged form. Distinctive Characteristics Single power supply operation Embedded Algorithms 2.7 to 3.6 V for read, program, and erase operations Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Manufactured on 200 m process technology Embedded Program algorithm automatically writes and verifies data High performance at specified addresses Access times as fast as 90 ns Compatibility with JEDEC standards Ultra low power consumption (typical values at 5 MHz) Pinout and software compatible with single-power supply Flash 200 nA Automatic Sleep mode current Superior inadvertent write protection 200 nA standby mode current CFI (Common Flash Interface) compliant 9mA read current Provides device-specific information to the system, allowing host 20 mA program/erase current software to easily reconfigure for different Flash devices Flexible sector architecture Data Polling and toggle bits Eight 8 Kbyte, sixty-three 64 Kbyte top or bottom boot block Provides a software method of detecting program or erase operation configurations available completion Supports full chip erase Ready/Busy pin (RY/BY ) Sector Protection Provides a hardware method of detecting program or erase cycle A hardware method of locking a sector to prevent any program or completion erase operations within that sector Erase Suspend/Erase Resume Sectors can be locked in-system or via programming equipment Suspends an erase operation to read data from, or program data to, Temporary Sector Unprotect feature allows code changes in a sector that is not being erased, then resumes the erase operation previously locked sectors Hardware reset pin (RESET ) Unlock Bypass Program Command Hardware method to reset the device to reading array data Reduces overall programming time when issuing multiple program command sequences 20-year typical data retention 1,000,000 cycle typical endurance per sector Tested to data sheet specifications at temperature Quality and reliability levels equivalent to standard packaged components Publication Number S29AL032D KGD SP Revision 02 Issue Date July 18, 2007Supplement S29AL032D Features The S29AL032D is a 32 Mbit, 3.0 volt-only Flash memory organized as 4,194,304 bytes or 2,097,152 words. The word-wide data (x16) appears on DQ15DQ0 the byte-wide (x8) data appears on DQ7DQ0. To eliminate bus contention, the device has separate chip enable (CE ), write enable (WE ) and output enable (OE ) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. No VPP is required for program or erase operations. The device can also be programmed in standard EPROM programmers. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY pin, or by reading the DQ7 (Data Polling) and DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. detector that automatically inhibits Hardware data protection measures include a low V CC write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET input terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Spansions Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 S29AL032D Known Good Die S29AL032D KGD SP 02 July 18, 2007

Tariff Desc

8542.32.00 32 No ..CMOS and MOS Read Only Memory and Programmable Read Only Memory whether erasable or non-erasable (for example, flash memory, EPROM, E2PROM, EAPROM, NOVRAM, ROM and PROM)
CYP
Cypress
Cypress / Spansion
CYPRESS SEMI
Cypress Semicon
Cypress Semiconductor
Cypress Semiconductor Corp
INF
INFINEON
Infineon IR
INFINEON (CYPRESS)
Infineon (IRF)
Infineon / Cypress
Infineon / IR
INFINEON TECH ICs
Infineon Technologies
INFINEON TECHNOLOGIES AG
Infineon Technologies Americas Corp.
Infinite Power Solutions
INTERNATIONAL RECTIF
INTERNATIONAL RECTIFIER
International Rectifier HiRel Products
INTL RECTIFIER
IR
IRH
Ramtron
Ramtron / Cypress Semiconductor
Ramtron International Corp
SP9
SPANSION

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