Low Skew, 1-to-2 8302 Data Sheet LVCMOS / LVTTL Fanout Buffer GENERAL DESCRIPTION FEATURES The 8302 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout 2 LVCMOS / LVTTL outputs Buffer. The 8302 hasa single ended clock input. The LVCMOS / LVTTL clock input accepts LVCMOS single endedclock input accepts LVCMOS or LVTTL or LVTTL input levels input levels. The 8302 features a pair of LVCMOS/ LVTTL outputs. The 8302 is characterized at full 3.3V for Maximum output frequency: 200MHz input V ,and mixed 3.3V and 2.5V for output operating DD Output skew: 25ps (typical) supply modes (V ). Guaranteed output and part-to-part DDO skew characteristics make the 8302 ideal for clock distribution Part-to-part skew: 250ps (typical) applications demanding well defined performance and Small 8 lead SOIC package saves board space repeatibility. Full 3.3V or 3.3V core, 2.5V supply modes 0C to 70C ambient operating temperature Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT VDDO Q0 Q0 1 8 VDD 2 7 GND CLK VDDO CLK 3 6 Q1 Q1 GND 4 5 8302 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 2016 Integrated Device Technology, Inc 1 Revision D March 4, 20168302 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6 V Power Output supply pins. DDO 2V Power Core supply pin. DD 3 CLK Input Pulldown LVCMOS / LVTTL clock input. 4,7 GND Power Power supply ground. 5 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V , V = 3.465V 22 pF Power Dissipation Capacitance DD DDO C PD (per output) V = 3.465V, V = 2.625V 16 pF DD DDO R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance 5 7 12 OUT 2016 Integrated Device Technology, Inc 2 Revision D March 4, 2016