Product Information


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Clock Buffers, Drivers VFBGA-52 RoHS
Manufacturer: Integrated Device Tech

Price (USD)

1: USD 4.0728 ea
Line Total: USD 4.0728

0 - Global Stock
MOQ: 1 Multiples:1
Pack Size :   1
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0 - Global Stock

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Wed. 05 Apr to Mon. 10 Apr

MOQ : 1
Multiples : 1

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Integrated Device Tech

1 : USD 4.0728
10 : USD 3.5331
30 : USD 3.1946
100 : USD 2.6576
364 : USD 2.4216
1092 : USD 2.3575

Integrated Device Tech
Product Category
Clock Drivers & Distribution
Clock Drivers Distribution
VFBGA - 52
Brand Category
Integrated Device Tech
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IDTCSPUA877A COMMERCIAL TEMPERATURE RANGE 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER 1.8V PHASE LOCKED LOOP IDTCSPUA877A DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER FEATURES: DESCRIPTION: 1 to 10 differential clock distribution The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer Optimized for clock distribution in DDR2 (Double Data Rate) to distribute one differential clock input pair(CLK, CLK ) to 10 differential SDRAM applications output pairs (Y 0:9 , Y 0:9 ) and one differential pair of feedback clock output Operating frequency: 125MHz to 410MHz (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization Stabilization time: <6us of the outputs to the input reference is provided. OE, OS, and AVDD control the Very low skew: 40ps power-down and test mode logic. When AVDD is grounded, the PLL is turned Very low jitter: 40ps off and bypassed for test mode purposes. When the differential clock inputs 1.8V AVDD and 1.8V VDDQ (CLK, CLK) are both at logic low, this device will enter a low power-down mode. CMOS control signal input In this mode, the receivers are disabled, the PLL is turned off, and the output Test mode enables buffers while disabling PLL clock drivers are disabled, resulting in a clock driver current consumption of less Low current power-down mode than 500A. Tolerant of Spread Spectrum input clock The CSPUA877A requires no external components and has been optimised Available in 52-Ball VFBGA and 40-pin VFQFPN packages for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPUA877 , designed for use in both module assemblies and system motherboard based APPLICATIONS: solutions, provides an optimum high-performance clock source. Meets or exceeds JEDEC standard CUA877 for registered DDR2 The CSPUA877A is available in Commercial Temperature Range (0C to clock driver +70C). See Ordering Information for details. Along with SSTUA32864/66, DDR2 register, provides complete solution for DDR2 DIMMs FUNCTIONAL BLOCK DIAGRAM LD orOE POWER OE DOWN AND LD, OS, or OE Y0 OS TEST MODE Y0 PLLBYPASS AVDD LOGIC Y1 LD Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK Y5 CLK Y5 10K-100K Y6 PLL Y6 FBIN Y7 FBIN Y7 Y8 Y8 Y9 Y9 NOTE: The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK. FBOUT FBOUT COMMERCIAL TEMPERATURE RANGE NOVEMBER 2008 1 c 2008 Integrated Device Technology, Inc. DSC 6872/5IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION 6 Y8 Y6 Y6 Y7 Y7 FBIN FBIN FBOUTFBOUT Y8 VDDQ GND 5 Y5 GND GND OS OE GND Y9 VDDQ VDDQ 4 GND Y5 GND NB NB NB Y9 NB VDDQ VDDQ 3 NB NB NB GND Y0 GND NB Y4 VDDQ VDDQ GND 2 Y0 GND GND GND Y4 VDDQ VDDQ VDDQ 1 Y1 Y1 Y2 Y2 CLK CLK Y3 Y3 AGND AVDD AB C D E G H JK F VFBGA TOP VIEW 52 BALL VFBGA PACKAGE LAYOUT 0.65mm 6 5 4 TOPVIEW 3 2 1 A B CDE F G H J K AB C D EF G H J K 1 2 3 4 5 6 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits