IS43/46QR16256A IS43/46QR85120A PRELIMINARY INFORMATION 512Mx8, 256Mbx16 4Gb DDR4 SDRAM JULY 2016 FEATURES Standard Voltage: VDD = VDDQ = 1.2V, VPP=2.5V Signal Integrity High speed data transfer rates with system frequency - Internal VREFDQ Training up to 2666 Mbps - Read Preamble Training Data Integrity - Gear Down Mode - Auto Self Refresh (ASR) by DRAM built-in TS - Per DRAM Adressability - Auto Refresh and Self Refresh Modes - Configurable DS for system compatibility DRAM access bandwidth - Configurable On-Die Termination - Separated IO gating structures by Bank Groups - Data bus Inversion (DBI) - Self Refresh Abort - ZQ Calibration for DS/ODT impedance accuracy via external - Fine Granularity Refresh ZQ pad (240 ohm +/- 1%) Signal Synchronization Power Saving and efficiency - Write Leveling via MR settings - POD with VDDQ termination - Read Leveling via MPR - Command/Address Latency (CAL) Reliability & Error Handling - Maximum Power Saving - Command/Address Parity - Low power Auto Self Refresh (LPASR) - Data bus Write CRC Operating Temperature - MPR readout o o - Commercial ( Tc = 0 C to + 95 C) - Boundary Scan (x16) o o - Industrial ( Tc = -40 C to + 95 C) Speed Grade (CL-TRCD-TRP) o o - Automotive A1 ( Tc = -40 C to + 95 C) - 2133Mbps / 15-15-15 (-093P) o o - Automotive A2 ( Tc = -40 C to + 105 C) - 2400Mbps / 16-16-16 (-083R) - 2666Mbps / 18-18-18 (-075U) ADDRESS TABLE PPROGRAMMABLE FUNCTIONS Output Driver Impedance (34/48) Parameter 512M x8 256M x16 CAS Write Latency (9/0/11/12/14/16/18) Row Addressing A0-A14 A0-A14 Additive Latency (0/CL-1/CL-2) CS to Command Address (3/4/5/6/8) A0-A9 A0-A9 Column Addressing Burst Type (Sequential/Interleaved) Write Recovery Time (10/12/14/16/18/20/24) Bank Addressing BA0-BA1 BA0-BA1 Read Preamble (1T/2T) Write Preamble (1T/2T) Bank Groups BG0-BG1 BG0-BG1 Burst Length (BL8/BC4/BC4 or 8 on the fly) Page size 1KB 2KB Options tRFC 260ns Configuration: 512Mx8, 256Mx16 Package: - 96-ball FBGA (9mm x 13mm, 0.8mm ball pitch) for x16 - 78-ball FBGA (9mm x 11mm, 0.8mm ball pitch) for x8 Copyright 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 Integrated Silicon Solution, Inc. - www.issi.com Rev. 0A, 06/22/2016 IS43/46QR16256A IS43/46QR85120A 1. DDR4 PACKAGE BALLOUT 1.1 DDR4 SDRAM package ball out 78-ball FBGA x8 (Top View) 2 Integrated Silicon Solution, Inc. - www.issi.com Rev. 0A, 06/22/2016