IS46TR16K01S2AL-125KBLA1

Long-term Support World Class Quality IS43/46LQ32256EA, IS43/46LQ32256EAL 8Gb (x16 x 2 channel ) Mobile LPDDR4/LPDDR4X with ECC DECEMBER 2021 FEATURES DESCRIPTION Configuration: The IS43/46LQ32256EA and IS43/46LQ32256EAL are - 256Mb x16 x 2 channels 8Gbit CMOS LPDDR4 SDRAM. The device is orga- - 8 internal banks per each channel nized as 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-da- On-Chip ECC: - Single-bit error correction (per 64-bits) ta-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N Low-voltage Core and I/O Power Supplies prefetch architecture with an interface designed to VDD1 = 1.70-1.95V transfer two data words per clock cycle at the I/O pins. VDD2 = 1.06-1.17V This product offers fully synchronous operations VDDQ = 1.06-1.17V (LPDDR4) referenced to both rising and falling edges of the clock. VDDQ = 0.57-0.65V (LPDDR4X) The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. LVSTL(Low Voltage Swing Terminated Logic) I/O Interface On-chip temperature sensor whose status Internal VREF and VREF Training can be read from MR4 Dynamic ODT : DQ ODT :VSSQ Termination 200-ball x32 BGA Package ( 10x14.5 mm) CA ODT :VSS Termination ADDRESS TABLE Max. Clock Frequency : 1.6GHz (3.2Gbps) Parameter 16n Pre-fetch DDR architecture of Channel 2 Single data rate (multiple cycles) command/ Row Addresses R0-R14 address bus Column Addresses C0-C9 Bidirectional/differential data strobe per byte of Bank Addresses BA0-BA2 data (DQS/DQS ) Note: Address information is per channel base. Programmable burst lengths (16 or 32) KEY TIMING PARAMETERS ZQ Calibration Operation Temperature Write Read Data Latency Latency Industrial (TC = -40C to 95C) Speed Freq. Rate Automotive, A1 (TC = -40C to 95C) Grade (MHz) Set Set DBI DBI (Mb/s) Automotive, A2 (TC = -40C to 105C) A B OFF ON Automotive, A3 (TC = -40C to 125C) -062 1600 3200 14 26 28 32 Clock-Stop capability -075 1333 2666 12 22 24 28 Note: Other clock frequencies/data rates supported please refer to AC timing tables. Copyright 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A2 12/17/2021 Long-term Support World Class Quality IS43/46LQ32256EA, IS43/46LQ32256EAL BALL ASSIGNMENTS AND DESCRIPTIONS 1. 200-ball x32 Discrete Package, 0.80mm x 0.65mm using MO-311 1 23 4 56 7 8 9 10 11 12 DNU/ NC A DNU DNU VSS VDD2 ZQ0 VDD2 VSS DNU 0.80mm Pitch ERR A B DNU DQ0 A VDDQ DQ7 A VDDQ VDDQ DQ15 A VDDQ DQ8 A DNU C VSS DQ1 A DMI0 A DQ6 A VSS VSS DQ14 A DMI1 A DQ9 A VSS D VDDQ VSS DQS0 T A VSS VDDQ VDDQ VSS DQS1 T A VSS VDDQ DQS0 C DQS1 C E VSS DQ2 A DQ5 A VSS VSS DQ13 A DQ10 A VSS A A F VDD1 DQ3 A VDDQ DQ4 A VDD2 VDD2 DQ12 A VDDQ DQ11 A VDD1 ODT CA G VSS VSS VDD1 VSS VSS VDD1 VSS NC VSS A (3) H VDD2 CA0 A NC CS0 A VDD2 VDD2 CA2 A CA3 A CA4 A VDD2 J VSS CA1 A VSS CKE0 A CK t A CK c A VSS CA5 A VSS NC K VDD2 VSS VDD2 VSS VSS VDD2 VSS VDD2 NC NC L M NC N VDD2 VSS VDD2 VSS VSS VDD2 VSS VDD2 NC P VSS CA1 B VSS CKE0 B NC CK T B CK C B VSS CA5 B VSS R VDD2 CA0 B CS0 B VDD2 VDD2 CA2 B CA3 B CA4 B VDD2 NC ODT CA T VSS VSS VDD1 VSS VSS VDD1 VSS RESET N VSS B (3) U VDD1 DQ3 B VDDQ DQ4 B VDD2 VDD2 DQ12 B VDDQ DQ11 B VDD1 DQS0 C DQS1 C V VSS DQ2 B DQ5 B VSS VSS DQ13 B DQ10 B VSS B B W VDDQ VSS DQS0 T B VSS VDDQ VDDQ VSS DQS1 T B VSS VDDQ Y VSS DQ1 B DMI0 B DQ6 B VSS VSS DQ14 B DMI1 B DQ9 B VSS AA DNU DQ0 B VDDQ DQ7 B VDDQ VDDQ DQ15 B VDDQ DQ8 B DNU DNU/ AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU ERR B NOTE 1 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows. NOTE 2 Top View, A1 in top left corner. NOTE 3 The ODT CA pin is ignored by LPDDR4X devices. NOTE 4 A11 will be ERR A. AB11 will be ERR B in optional B2 package. Integrated Silicon Solution, Inc. www.issi.com 2 Rev. A2 12/17/2021 0.65mm Pitch