Product Information

PDM41024LA15S0ITR

PDM41024LA15S0ITR electronic component of IXYS

Datasheet
SRAM Chip Async Single 5V 1M-bit 128K x 8 15ns 32-Pin SOJ T/R
Manufacturer: IXYS
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

750: USD 7.169 ea
Line Total: USD 5376.75

0 - Global Stock
MOQ: 750  Multiples: 750
Pack Size: 750

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Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 750
Multiples : 750
750 : USD 7.169

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Access Time
Maximum Clock Frequency
Mounting Style
Packaging
Brand
Density
Number Of Ports
Supply Current
Number Of Words
Architecture
Address Bus
Operating Temp Range
Rad Hardened
Word Size
Operating Supply Voltage Typ
Operating Supply Voltage Min
Operating Supply Voltage Max
Sync/Async
Operating Temperature Classification
Package Type
Pin Count
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Additional Infomation About Product

PDM41024 1 Megabit Static RAM 128K x 8-Bit 1 Features Description n High-speed access times The PDM41024 is a high-performance CMOS static Coml: 10, 12 and 15 ns RAM organized as 131,072 x 8 bits. Writing is 2 accomplished when the write enable (WE) and the Indl: 12 and 15 ns chip enable (CE1) inputs are both LOW and CE2 is n Low power operation (typical) HIGH. Reading is accomplished when WE and CE2 - PDM41024SA remain HIGH and CE1 and OE are both LOW. 3 Active: 450 mW The PDM41024 operates from a single +5V power Standby: 50 mW supply and all the inputs and outputs are fully TTL- - PDM41024LA compatible. The PDM41024 comes in two versions: Active: 400 mW the standard power version (SA) and the low power 4 Standby: 25mW version (LA). The two versions are functionally the same and differ only in their power consumption. n Single +5V ( 10%) power supply The PDM41024 is available in a 32-pin plastic TSOP n TTL-compatible inputs and outputs 5 (I), and a 300-mil and 400-mil plastic SOJ. n Packages Plastic SOJ (300 mil) - TSO Plastic SOJ (400 mil) - SO Plastic TSOP (I)- T 6 Functional Block Diagram 7 A 0 Decoder Memory 8 Addresses Matrix A 16 9 I/O 0 Input Column I/O Data Control 10 I/O 7 11 CE1 CE2 Control WE 12 OE Rev. 3.3 - 4/09/98 1 PDM41024 Pin Conguration TSOP (I) SOJ Vcc NC 1 32 A11 1 32 OE 2 A9 31 A10 2 A15 A16 31 3 A8 30 CE1 30 CE2 A14 3 A13 4 29 I/O7 29 WE A12 4 5 WE 28 I/O6 A7 5 A13 6 28 CE2 27 I/O5 A15 7 26 I/O4 A6 6 A8 27 Vcc 8 25 I/O3 A5 7 26 A9 9 NC 24 Vss A4 8 25 A11 10 A16 23 I/O2 A3 9 24 OE A14 11 22 I/O1 12 A12 21 I/O0 A2 10 23 A10 13 A7 20 A0 11 CE1 A1 22 A6 14 19 A1 12 21 I/O7 A0 15 A5 18 A2 13 20 I/O6 16 I/O0 A4 17 A3 14 19 I/O5 I/O1 15 18 I/O2 I/O4 Pin Description 16 17 Vss I/O3 Name Description (1) Truth Table A16-A0 Address Inputs OE WE CE1 CE2 I/O MODE I/O7-I/O0 Data Inputs/Outputs OE Output Enable Input X X H X Hi-Z Standby WE Write Enable Input X X X L Hi-Z Standby CE1, CE2 Chip Enable Inputs LH L H D Read OUT NC No Connect XL L H D Write IN H H L H Hi-Z Output Disable V Power (+5V) CC V Ground SS NOTE: 1. H = V , L = V , X = DONT CARE IH IL (1) Absolute Maximum Ratings Symbol Rating Coml. Ind. Unit V Terminal Voltage with Respect to V 0.5 to +7.0 0.5 to +7.0 V TERM SS T Temperature Under Bias 55 to +125 65 to +135 C BIAS T Storage Temperature 55 to +125 65 to +150 C STG P Power Dissipation 1.0 1.0 W T I DC Output Current 50 50 mA OUT (2) T Maximum Junction Temperature 125 145 C j NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specically for those where the chosen package has a large thermal resistance (e.g., TSOP). The cal- culation should be of the form: T = T + P * q where T is the ambient temperature, P j a ja a is average operating power and q the thermal resistance of the package. For this ja product, use the following q values: ja o SOJ: 72 C/W o TSOP: 95 C/W 2 4/09/98 - Rev. 3.3

HS Compliance

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory

IXYS may also be referenced as

CLR
IXS
IXYS
IXYS CORP
Ixys Corporation
IXYS INTEG.CIRCUITS DIV(CLARE)
IXYS Integrated Circuits
IXYS Integrated Circuits / Clare
IXYS Integrated Circuits Division
IXYS Integrated Circuits/Clare
IXYS RF
IXYS SEMICONDUCTOR

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