Revision 10 eX Family FPGAs Single-Chip Solution Leading Edge Performance Nonvolatile 240 MHz System Performance Live on Power-Up 350 MHz Internal Performance No Power-Up/Down Sequence Required for Supply 3.9 ns Clock-to-Out (Pad-to-Pad) Voltages Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up Specifications Individual Output Slew Rate Control 3,000 to 12,000 Available System Gates 2.5V, 3.3V, and 5.0V Mixed-Voltage Operation with Maximum 512 Flip-Flops (Using CC Macros) 5.0V Input Tolerance and 5.0V Drive Strength 0.22 m CMOS Process Technology Software Design Support with Microsemi Designer and Libero Integrated Design Environment (IDE) Tools Up to 132 User-Programmable I/O Pins Up to 100% Resource Utilization with 100% Pin Locking Deterministic Timing Features Unique In-System Diagnostic and Verification Capability with Silicon Explorer II High-Performance, Low-Power Antifuse FPGA Boundary Scan Testing in Compliance with IEEE LP/Sleep Mode for Additional Power Savings Standard 1149.1 (JTAG) Advanced Small-Footprint Packages Fuselock Secure Programming Technology Designed Hot-Swap Compliant I/Os to Prevent Reverse Engineering and Design Theft Product Profile Device eX64 eX128 eX256 Capacity 3,000 6,000 12,000 System Gates 2,000 4,000 8,000 Typical Gates Register Cells Dedicated Flip-Flops 64 128 256 Maximum Flip-Flops 128 256 512 Combinatorial Cells 128 256 512 Maximum User I/Os 84 100 132 Global Clocks Hardwired 1 1 1 Routed 2 2 2 Speed Grades F, Std, P F, Std, P F, Std, P Temperature Grades* C, I, A C, I, A C, I, A Package (by pin count) TQ 64, 100 64, 100 100 Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings. October 2012 I 2012 Microsemi CorporationOrdering Information eX128 P TQ G 100 Application (Ambient Temperature Range) Blank = Commercial (0C to 70C) I = Industrial (-40C to 85C) A = Automotive (-40C to 125C) PP = Pre-production Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type = TQ Thin Quad Flat Pack (0.5 mm pitch) Speed Grade Blank = Standard Speed P = Approximately 30% Faster than Standard F = Approximately 40% Slower than Standard Part Number eX64 = 64 Dedicated Flip-Flops (3,000 System Gates) eX128 = 128 Dedicated Flip-Flops (6,000 System Gates) eX256 = 256 Dedicated Flip-Flops (12,000 System Gates) eX Device Status eX Devices Status eX64 Production eX128 Production eX256 Production Plastic Device Resources User I/Os (Including Clock Buffers) Device TQ64 TQ100 eX64 41 56 eX128 46 70 eX256 81 Note: TQ = Thin Quad Flat Pack II Revision 10