MAX3674 19-2483 Rev 0 12/07 E V A L U A T I O N K I T A V A I L A B L E High-Performance, Dual-Output, Network Clock Synthesizer General Description Features The MAX3674 is a high-performance network clock 21.25MHz to 1360MHz Programmable PLL Synthe- synthesizer IC for networking, computing, and telecom sized Output Clocks applications. It integrates a crystal oscillator, a low- Two Differential LVPECL-Compatible Outputs noise phase-locked loop (PLL), programmable dividers, and high-frequency LVPECL output buffers. The PLL Cycle-to-Cycle Jitter 1.6ps RMS and Period Jitter generates a high-frequency clock based on a low-fre- 0.9ps RMS at 500MHz quency reference clock provided by the on-chip crystal On-Chip Crystal Oscillator or Selectable oscillator or an external LVCMOS clock. The MAX3674 has excellent period jitter, cycle-to-cycle jitter, and sup- LVCMOS-Compatible Reference Clock Input ply noise rejection performance. With output frequen- Excellent Power-Supply Noise Rejection cies programmable from 21.25MHz to 1360MHz and 2 support of two differential PECL output signals, the Parallel or 2-Wire I C Programming Interface device provides a versatile solution for the most Lock Indicator Output demanding clock applications. 2 +3.3V Power Supply Programming is accomplished through a 2-wire I C bus or parallel interface that can change the output fre- Power Consumption: 396mW at 3.3V quency on demand for frequency margining. Both 48-Pin LQFP Pb-Free Package LVPECL outputs have synchronous stop functionality, and the PLL has a LOCK indicator output. The -40C to +85C Temperature Range MAX3674 operates from a +3.3V supply and typically consumes 396mW. The device is packaged in a 48-pin Ordering Information LQFP, and the operating temperature range is from -40C to +85C. PART TEMP RANGE PIN-PACKAGE MAX3674ECM+ -40C to +85C 48 LQFP Applications +Denotes a lead-free/RoHS-compliant package. Ethernet Network ASIC Clock Generation Storage Area Network ASIC Clocking Optical Network ASIC Clocking Pin Configuration appears at end of data sheet. Programmable Clock Source for Server, Comput- ing, or Communication Systems Frequency Margining Typical Application Circuit +3.3V +3.3V +3.3V +3.3V LVPECL OUTPUTS 130 REF SEL V V CC CC PLL Z = 50 REF CLK QA QA NETWORK XTAL1 ASIC QB 16MHz QB XTAL2 MAX3674 82 2 SERIAL I C SDA CLK STOPA INTERFACE SCL +3.3V M 9:0 CLK STOPB PARALLEL NA 2:0 BYPASS INTERFACE NB P PLL DIVIDER CONTROLS PLOAD MR GND LOCK Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.High-Performance, Dual-Output, Network Clock Synthesizer ABSOLUTE MAXIMUM RATINGS Supply Voltage Range (V and V )...........-0.3V to +3.9V DC Input Current...............................................................20mA CC CC PLL DC Input Voltage Range (BYPASS, REF SEL, DC Output Current............................................................50mA Continuous Power Dissipation (T = +70C) REF CLK, CLK STOPx, XTAL1, XTAL2, A 48-Pin LQFP (derate 21.7mW/C above 70C) ..........1739mW M 9:0 , TEST EN, NB, NA 2:0 , PLOAD, Operating Ambient Temperature Range (T )......-40C to +85C MR, SDA, SCL, ADR 1:0 , P) to GND......-0.3V to (V + 0.3V) A CC Operating Junction Temperature (T )..............................+150C J DC Output Voltage Range (LOCK, SDA, Storage Temperature Range .............................-65C to +150C Qx, Qx) ....................................................-0.3V to (V + 0.3V) CC Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V = V = +3.3V 5%, T = -40C to +85C, BYPASS = high, TEST EN = low. Typical values are at V = V = +3.3V, CC CC PLL A CC CC PLL T = +25C, unless otherwise noted.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS INPUTS (BYPASS, REF SEL, REF CLK, CLK STOPx, M 9:0 , TEST EN, NB, NA 2:0 , PLOAD, MR, ADR 1:0 , P) V + CC Input High Voltage V 2.0 V IH 0.3 Input Low Voltage V -0.3 +0.8 V IL Input Current I , I V = V or GND (Note 2) 200 A IH IL IN CC Input Capacitance C 4.0 pF IN 2 I C INPUTS (SDA, SCL) V + CC Input High Voltage V 2.0 V IH 0.3 Input Low Voltage V -0.3 +0.8 V IL Input Current I , I V = V or GND 10 A IH IL IN CC 2 I C OPEN-DRAIN OUTPUT (SDA) Output Low Voltage V I = +4mA 0.4 V OL OL LVCMOS/TTL OUTPUT (LOCK) Output High Voltage V I = -4mA 2.4 V OH OH Output Low Voltage V I = +4mA 0.4 V OL OL LVPECL DIFFERENTIAL CLOCK OUTPUTS (Qx, Qx) V - V - CC CC Output High Voltage V (Note 3) V OH 1.25 0.74 V - V - CC CC Output Low Voltage V (Note 3) V OL 1.95 1.45 POWER SUPPLY Supply Voltage V 3.135 3.3 3.465 V CC PLL Supply Voltage V (Note 4) 3.035 3.3 3.465 V CC PLL Includes PECL output currents (Note 3) 120 136 Supply Current I mA CC PECL outputs open 81 PLL Supply Current I 10 mA CC PLL 2 MAX3674