VN4012 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description This enhancement-mode (normally-off) transistor utilizes Free from secondary breakdown a vertical DMOS structure and Supertexs well-proven, Low power drive requirement silicon-gate manufacturing process. This combination Ease of paralleling produces a device with the power handling capabilities Low C and fast switching speeds ISS of bipolar transistors and the high input impedance and Excellent thermal stability positive temperature coefcient inherent in MOS devices. Integral source-drain diode Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary High input impedance and high gain breakdown. Applications Supertexs vertical DMOS FETs are ideally suited to a Motor controls wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high Converters input impedance, low input capacitance, and fast switching Ampliers speeds are desired. Switches Power supply circuits Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Ordering Information R I V Package Option DS(ON) D(ON) GS(TH) BV /BV DSS DGS Device (max) (max) (min) (V) TO-92 (V) () (mA) VN4012 VN4012L-G 400 12 1.8 150 -G indicates package is RoHS compliant (Green) Pin Conguration DRAIN SOURCE Absolute Maximum Ratings Parameter Value GATE Drain-to-source voltage BV TO-92 (L) DSS Drain-to-gate voltage BV DGS Product Marking Gate-to-source voltage 20V O O Operating and storage temperature -55 C to +150 C Si VN YY = Year Sealed 4 0 1 2 L O WW = Week Sealed Soldering temperature* 300 C YYWW = Green Packaging Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous Package may or may not include the following marks: Si or operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. TO-92 (L) * Distance of 1.6mm from case for 10 seconds. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.comVN4012 Thermal Characteristics I I Power Dissipation D D I I jc ja DR DRM O Package (continuous) (pulsed) T = 25 C O O C ( C/W) ( C/W) (mA) (mA) (mA) (mA) (W) TO-92 160 650 1.0 125 170 160 650 Notes: I (continuous) is limited by max rated T . D j O Electrical Characteristics (T = 25 C unless otherwise specied) A Sym Parameter Min Typ Max Units Conditions BV Drain-to-source breakdown voltage 400 - - V V = 0V, I = 100A DSS GS D V Gate threshold voltage 0.6 - 1.8 V V = V , I = 1.0mA GS(th) GS DS D I Gate body leakage - - 10 nA V = 20V, V = 0V GSS GS DS - - 1 V = 0V, V = 0.8 Max Rating GS DS I Zero gate voltage drain current A V = 0.8 Max Rating, DSS DS - - 100 V = 0V, T = 125C GS A I On-state drain current 0.15 0.3 - A V = 4.5V, V = 10V D(ON) GS DS - 9.5 12 V = 4.5V, I = 100mA Static drain-to-source on-state GS D R DS(ON) O resistance - 17 30 V = 4.5V, I = 100mA, T = 125 C GS D A G Forward transductance 125 350 - mmho V = 15V, I = 100mA FS DS D C Input capacitance - - 110 ISS V = 0V, GS C Common source output capacitance - - 30 pF V = 25V, OSS DS f = 1.0MHz C Reverse transfer capacitance - - 10 RSS t Rise time - - 20 r V = 25V, t Turn-on delay time - - 20 DD d(ON) ns I = 100mA, D t Fall time - - 65 f R = 25 GEN t Turn-off delay time - - 65 d(OFF) V Diode forward voltage drop - - 1.2 V V = 0V, I = 160mA SD GS SD Notes: O 1. All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit V DD 10V 90% R L INPUT PULSE GENERATOR 10% 0V OUTPUT t t (ON) (OFF) R GEN t t t t d(ON) d(OFF) r F V DD D.U.T. 10% 10% INPUT OUTPUT 0V 90% 90% 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2