Register Map: Section 6.2 ZL30252, ZL30253 3-Input, 3-Output Any-to-Any Clock Multiplier and Jitter Attenuator ICs Data Sheet January 2018 Ordering Information Features ZL30252LDG1 32 Pin QFN Trays Input Clocks ZL30252LDF1 32 Pin QFN Tape and Reel Three inputs: two differential/CMOS, one CMOS ZL30253LDG1 32 Pin QFN Trays ZL30253LDF1 32 Pin QFN Tape and Reel Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS) Matte Tin Inputs continually monitored for activity and Package size: 5 x 5 mm frequency accuracy -40 C to +85 C Automatic or manual reference switching Low-Bandwidth DPLL Per-output supply pin with CMOS output voltages from 1.5V to 3.3V Programmable bandwidth, 14Hz to 500Hz Precise output alignment circuitry and per- Attenuates jitter up to several UI output phase adjustment Freerun or digital hold on loss of all inputs Per-output enable/disable and glitchless Digitally controlled phase adjustment start/stop (stop high or low) Low-Jitter Fractional-N APLL and 3 Outputs General Features Any output frequency from <1Hz to 1035MHz Automatic self-configuration at power-up from external (ZL30252) or internal (ZL30253) High-resolution fractional frequency conversion EEPROM up to four configs pin-selectable with 0ppm error Numerically controlled oscillator mode Easy-to-configure, encapsulated design requires no external VCXO or loop filter Spread-spectrum modulation mode components Zero-delay mode with external feedback Each output has independent dividers 2 SPI or I C processor Interface Output jitter is typically 0.16 to 0.28ps RMS Easy-to-use evaluation software (12kHz-20MHz integration band) Applications Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL Frequency conversion, jitter attenuation and frequency synthesis in a wide variety of In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz) equipment types IC1P, IC1N OC1P, OC1N HSDIV1 HSDIV1 DIV1 Input Block DPLL APLL VDDO1 Divider, Jitter Filtering, ~3.7 to 4.2GHz, IC2P, IC2N OC2P, OC2N HSDIV2 Monitor, Digital Hold DIV2 Fractional-N Selector VDDO2 IC3P/GPIO3 OC3P, OC3N HSDIV3 Figure 10 Figure 11 Figure 12 HSDIV2 DIV3 VDDO3 Microprocessor Port (SPI or I2C Serial) XA xtal and HW Control and Status Pins driver 2 XB Figure 1 - Functional Block Diagram 1 Microsemi Confidential Copyright 2018. Microsemi Corporation. All Rights Reserved. RSTN AC0/GPIO0 AC1/GPIO1 TEST/GPIO2 IC3P/GPIO3 IF0/CSN IF1/MISO SCL/SCLK SDA/MOSI ZL30252, ZL30253 Data Sheet Table of Contents 1. APPLICATION EXAMPLES .......................................................................................................... 6 2. DETAILED FEATURES ................................................................................................................. 6 2.1 INPUT BLOCK FEATURES ............................................................................................................... 6 2.2 DPLL FEATURES .......................................................................................................................... 6 2.3 APLL FEATURES .......................................................................................................................... 7 2.4 OUTPUT CLOCK FEATURES ........................................................................................................... 7 2.5 GENERAL FEATURES .................................................................................................................... 7 2.6 EVALUATION SOFTWARE ............................................................................................................... 7 3. PIN DIAGRAM ............................................................................................................................... 8 4. PIN DESCRIPTIONS ..................................................................................................................... 9 5. FUNCTIONAL DESCRIPTION .................................................................................................... 11 5.1 DEVICE IDENTIFICATION .............................................................................................................. 11 5.2 TOP-LEVEL CONFIGURATION ....................................................................................................... 11 5.2.1 APLL-Only Mode .................................................................................................................................. 11 5.2.2 DPLL+APLL Mode ............................................................................................................................... 12 5.2.3 Evaluation Software for Device Configuration ..................................................................................... 13 5.3 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ........................................................... 13 5.3.1 ZL30252External EEPROM or No EEPROM ................................................................................... 13 5.3.2 ZL30253Internal EEPROM ............................................................................................................... 14 5.4 LOCAL OSCILLATOR OR CRYSTAL ................................................................................................ 14 5.4.1 External Oscillator ................................................................................................................................ 15 5.4.2 External Crystal and On-Chip Driver Circuit ........................................................................................ 15 5.4.3 Clock Doubler ....................................................................................................................................... 16 5.4.4 Ring Oscillator (for System Start-Up) ................................................................................................... 16 5.5 INPUT SIGNAL FORMAT CONFIGURATION ...................................................................................... 17 5.6 INPUT BLOCK: INPUT DIVIDER, MONITOR AND SELECTOR .............................................................. 17 5.6.1 Input Clock Inversion and High-Speed Dividers .................................................................................. 17 5.6.2 Input Clock Monitoring ......................................................................................................................... 18 5.6.2.1 External Monitoring ....................................................................................................................... 18 5.6.2.2 Monitor Priority and Validation Timer............................................................................................ 18 5.6.2.3 Input Monitor Configuration .......................................................................................................... 19 5.6.3 Input Clock Priority, Selection and Switching for the DPLL ................................................................. 19 5.6.3.1 Priority Configuration .................................................................................................................... 19 5.6.3.2 Automatic Selection ...................................................................................................................... 19 5.6.3.3 Manual Selection .......................................................................................................................... 20 5.6.3.4 External Reference Switching Mode............................................................................................. 20 5.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 20 5.7.1 DPLL Configuration .............................................................................................................................. 21 5.7.2 DPLL States ......................................................................................................................................... 21 5.7.3 DPLL Capabilities ................................................................................................................................. 21 5.7.4 Input Wander and Jitter Tolerance ....................................................................................................... 22 5.7.5 Jitter and Wander Transfer .................................................................................................................. 22 5.7.6 Output Jitter and Wander ..................................................................................................................... 22 5.7.7 Numerically Controlled Oscillator (NCO) Mode ................................................................................... 22 5.7.8 Spread-Spectrum Modulation Mode .................................................................................................... 23 5.8 APLL CONFIGURATION ............................................................................................................... 23 5.8.1 APLL Input Selection and Frequency .................................................................................................. 23 5.8.1.1 APLL-Only Mode........................................................................................................................... 23 2 Microsemi Confidential