Register Map: Section 5.2 TM ZL40250 ZL40253 SmartBuffer 6- or 10-Output Programmable Fanout Buffers with Multi-Format I/O and Dividers Data Sheet September 2020 Features Ordering Information Four Flexible Input Clocks ZL40250LDG1 ext. EEPROM 6 Outputs Trays ZL40250LDF1 ext. EEPROM 6 Outputs Tape and Reel One crystal/CMOS input ZL40251LDG1 int. EEPROM 6 Outputs Trays ZL40251LDF1 int. EEPROM 6 Outputs Tape and Reel Two differential/CMOS inputs ZL40252LDG1 ext. EEPROM 10 Outputs Trays ZL40252LDF1 ext. EEPROM 10 Outputs Tape and Reel One single-ended/CMOS input ZL40253LDG1 int. EEPROM 10 Outputs Trays ZL40253LDF1 int. EEPROM 10 Outputs Tape and Reel Any input frequency up to 1GHz (300MHz for Matte Tin CMOS) Package size: 8 x 8 mm, 56 Pin QFN -40 C to +85 C Manual clock switching by pin or register 6 or 10 Universal Output Clocks with Dividers General Features Each output has independent divider Automatic self-configuration at power-up from external (ZL40250 or 2) or internal (ZL40251 or 3) Low additive jitter <200fs RMS (12kHz-20MHz, EEPROM up to 8 configurations pin-selectable for input frequencies 100MHz) PCIe 1, 2, 3, 4 compliant Each output configurable as LVDS, LVPECL, HCSL, 2xCMOS or HSTL Four multi-purpose I/O pins 2 In 2xCMOS mode, the P and N pins can be SPI or I C processor Interface * different frequencies (e.g. 125MHz and 25MHz) Core supply voltage options: 2.5V only, 3.3V Multiple output supply voltage banks with only, 1.8V+2.5V or 1.8V+3.3V CMOS output voltages from 1.5V to 3.3V Space-saving 8x8mm QFN56 (0.5mm pitch) Precise output alignment circuitry from GPIO Easy-to-use evaluation/programming software * pin or register bit Applications * Per-output skew adjustment Clock signal fanout, format conversion, frequency Per-output enable/disable and glitchless division and skew adjustment in a wide variety of * start/stop (stop high or low) equipment types VDDOA OC1P, OC1N DIV1 DIV IC1P, IC1N Path 1 DIV IC2P, IC2N OC2P, OC2N DIV2 DIV IC3P VDDOB XA xtal Path 2 DIV OC3P, OC3N DIV3 driver XB VDDOC OC4P, OC4N DIV4 OC5P, OC5N DIV5 VDDOD 10-output OC6P, OC6N devices only DIV6 RSTN AC0/GPIO0 OC7P, OC7N DIV7 AC1/GPIO1 Microprocessor VDDOE AC2/GPIO2 Port OC8P, OC8N DIV8 TEST/GPIO3 (SPI or I2C Serial) VDDOF IF0/CSN OC9P, OC9N DIV9 and GPIO Pins IF1/MISO SCL/SCLK OC10P, OC10N DIV10 SDA/MOSI Figure 1 - Functional Block Diagram * some features require a higher-frequency input clock and enabling the output dividers 1 Microsemi Confidential Copyright 2020. Microsemi Corporation. All Rights Reserved. ZL40250-ZL40253 Data Sheet Table of Contents 1. APPLICATION EXAMPLES .......................................................................................................... 4 2. PIN DIAGRAM ............................................................................................................................... 4 3. PIN DESCRIPTIONS ..................................................................................................................... 5 4. FUNCTIONAL DESCRIPTION ...................................................................................................... 7 4.1 DEVICE IDENTIFICATION ................................................................................................................ 7 4.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ............................................................. 7 4.2.1 ZL40250 and ZL40252 Internal ROM, External or No EEPROM ........................................................ 8 4.2.2 ZL40251 and ZL40253 Internal EEPROM .......................................................................................... 8 4.3 LOCAL OSCILLATOR OR CRYSTAL .................................................................................................. 9 4.3.1 External Oscillator .................................................................................................................................. 9 4.3.2 External Crystal and On-Chip Driver Circuit .......................................................................................... 9 4.3.3 Ring Oscillator (for Auto-Configuration) ............................................................................................... 10 4.4 INPUT SIGNAL FORMAT CONFIGURATION ...................................................................................... 10 4.5 PATH 1 AND PATH 2 SIGNAL SELECTION ...................................................................................... 10 4.6 OUTPUT CLOCK CONFIGURATION ................................................................................................ 10 4.6.1 Output Enable, Signal Format, Voltage and Interfacing ...................................................................... 11 4.6.2 Output Frequency Configuration .......................................................................................................... 11 4.6.3 Output Duty Cycle Adjustment ............................................................................................................. 12 4.6.4 Output Phase Adjustment .................................................................................................................... 12 4.6.5 Output-to-Output Phase Alignment ...................................................................................................... 12 4.6.6 Output Clock Start and Stop ................................................................................................................ 13 4.7 MICROPROCESSOR INTERFACE ................................................................................................... 14 4.7.1 SPI Slave ............................................................................................................................................. 14 4.7.2 SPI Master (ZL40250 and ZL40252 Only) ........................................................................................... 16 2 4.7.3 I C Slave .............................................................................................................................................. 17 4.8 INTERRUPT LOGIC ...................................................................................................................... 19 4.9 RESET LOGIC ............................................................................................................................. 20 4.10 POWER-SUPPLY CONSIDERATIONS .......................................................................................... 20 4.11 AUTO-CONFIGURATION FROM EEPROM OR ROM .................................................................... 20 4.11.1 Generating Device Configurations ....................................................................................................... 21 4.11.2 Direct EEPROM Write Mode (ZL40251 and ZL40253 Only) ............................................................... 21 4.11.3 Holding Other Devices in Reset During Auto-Configuration ................................................................ 21 4.12 CONFIGURATION SEQUENCE .................................................................................................... 21 4.13 POWER SUPPLY DECOUPLING AND LAYOUT RECOMMENDATIONS ............................................... 21 5. REGISTER DESCRIPTIONS ....................................................................................................... 21 5.1 REGISTER TYPES ....................................................................................................................... 21 5.1.1 Status Bits ............................................................................................................................................ 21 5.1.2 Configuration Fields ............................................................................................................................. 22 5.1.3 Bank-Switched Registers (ZL40251 and ZL40253 Only) .................................................................... 22 5.2 REGISTER MAP .......................................................................................................................... 23 5.3 REGISTER DEFINITIONS .............................................................................................................. 25 5.3.1 Global Configuration Registers ............................................................................................................ 25 5.3.2 Status Registers ................................................................................................................................... 32 5.3.3 Path 1 Configuration Registers ............................................................................................................ 38 5.3.4 Path 2 Configuration Registers ............................................................................................................ 39 5.3.5 Output Clock Configuration Registers .................................................................................................. 40 5.3.6 Input Clock Configuration Registers .................................................................................................... 45 6. ELECTRICAL CHARACTERISTICS ........................................................................................... 47 2 Microsemi Confidential