4Gb: x4, x8, x16 DDR4 SDRAM
Features
DDR4 SDRAM
MT40A1G4
MT40A512M8
MT40A256M16
1
Options Marking
Features
Configuration
V = V = 1.2V 60mV
DD DDQ
1 Gig x 4 1G4
V = 2.5V, 125mV/+250mV
PP
512 Meg x 8 512M8
On-die, internal, adjustable V generation
2
REFDQ
256 Meg x 16 256M16
1.2V pseudo open-drain I/O
FBGA package (Pb-free) x4, x8
T maximum up to 95C
C
78-ball (9mm x 11.5mm) Rev. A HX
64ms, 8192-cycle refresh up to 85C
78-ball (9mm x 10.5mm) Rev. B RH
32ms, 8192-cycle refresh at >85C to 95C
78-ball (8mm x 12mm) Rev. E WE
16 internal banks (x4, x8): 4 groups of 4 banks each
78-ball (7.5mm x 11mm) Rev. F SA
8 internal banks (x16): 2 groups of 4 banks each
FBGA package (Pb-free) x16
8n-bit prefetch architecture
96-ball (9mm x 14mm) Rev. A HA
Programmable data strobe preambles
96-ball (9mm x 14mm) Rev. B GE
Data strobe preamble training
96-ball (7.5mm x 13.5mm) Rev. E, F LY
Command/Address latency (CAL)
Timing cycle time
Multipurpose register READ and WRITE capability
0.625ns @ CL = 22 (DDR4-3200) -062E
Write leveling
0.682ns @ CL = 20 (DDR4-2933) -068E
Self refresh mode
0.682ns @ CL = 21 (DDR4-2933) -068
Low-power auto self refresh (LPASR)
0.750ns @ CL = 18 (DDR4-2666) -075E
Temperature controlled refresh (TCR)
0.750ns @ CL = 19 (DDR4-2666) -075
Fine granularity refresh
0.833ns @ CL = 16 (DDR4-2400) -083E
Self refresh abort
0.833ns @ CL = 17 (DDR4-2400) -083
Maximum power saving
0.937ns @ CL = 15 (DDR4-2133) -093E
Output driver calibration
0.937ns @ CL = 16 (DDR4-2133) -093
Nominal, park, and dynamic on-die termination
1.071ns @ CL = 13 (DDR4-1866) -107E
(ODT)
Operating temperature
Data bus inversion (DBI) for data bus
Commercial (0 T 95C) None
C
Command/Address (CA) parity
Industrial (40 T 95C) IT
C
Databus write cyclic redundancy check (CRC)
Revision :A
Per-DRAM addressability
:B
Connectivity test
:E
sPPR and hPPR capability
:F
JEDEC JESD-79-4 compliant
1. Not all options listed can be combined to
Notes:
define an offered product. Use the part
catalog search on 4Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 1: Key Timing Parameters
1 t t t t
Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns)
-062Y 3200 22-22-22 13.75 (13.32) 13.75 (13.32) 13.75 (13.32)
-062E 3200 22-22-22 13.75 13.75 13.75
-068 2933 21-21-21 14.32 (13.75) 14.32 (13.75) 14.32 (13.75)
-075E 2666 18-18-18 13.50 13.50 13.50
-075 2666 19-19-19 14.25 14.25 14.25
-083E 2400 16-16-16 13.32 13.32 13.32
-083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75)
-093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50)
-093 2133 16-16-16 15.00 15.00 15.00
-107E 1866 13-13-13 13.92 (13.50) 13.92 (13.50) 13.92 (13.50)
Note: 1. Refer to the Speed Bin Tables for additional details.
Table 2: Addressing
Parameter 1024 Meg x 4 512 Meg x 8 256 Meg x 16
Number of bank groups 4 4 2
Bank group address BG[1:0] BG[1:0] BG0
Bank count per group 4 4 4
Bank address in bank group BA[1:0] BA[1:0] BA[1:0]
Row addressing 64K (A[15:0]) 32K (A[14:0]) 32K (A[14:0])
Column addressing 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0])
1 2
Page size 512B / 1KB 1KB 2KB
Notes: 1. Page size is per bank, calculated as follows:
COLBITS
Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
2. Die revision dependant.
CCMTD-1725822587-9046 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
4gb_ddr4_dram.pdf - Rev. K 06/18 EN 2014 Micron Technology, Inc. All rights reserved.