74AHC02-Q100; 74AHCT02-Q100
Quad 2-input NOR gate
Rev. 2 11 May 2020 Product data sheet
1. General description
The 74AHC02-Q100; 74AHCT02-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC
standard No. 7-A.
The 74AHC02-Q100; 74AHCT02-Q100 provides a quad 2-input NOR function.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 C to +85 C and from -40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC02-Q100: CMOS level
For 74AHCT02-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC02D-Q100 -40 C to +125 C SO14 plastic small outline package; 14 leads; SOT108-1
body width 3.9 mm
74AHCT02D-Q100
74AHC02PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
74AHCT02PW-Q100
74AHC02BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1
enhanced very thin quad flat package; no leads;
74AHCT02BQ-Q100
14 terminals; body 2.5 3 0.85 mmNexperia
74AHC02-Q100; 74AHCT02-Q100
Quad 2-input NOR gate
4. Functional diagram
2
2 1A
1
1
1Y 1
3
3 1B
5
5 2A
1
2Y 4 4
6
6 2B
8 3A 8
3Y 10
1
10
9 3B
9
A
11 4A
11
4Y 13
Y
1
12 4B 13
12
B
mna216 001aah084 mna215
Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate)
5. Pinning information
5.1. Pinning
74AHC02-Q100
74AHCT02-Q100
terminal 1
index area
1A 2 13 4Y
1B 3 12 4B
74AHC02-Q100
2Y 4 11 4A
74AHCT02-Q100
5 10
2A (1) 3Y
GND
1Y 1 14 V
CC
2B 6 9 3B
2 13
1A 4Y
3 12
1B 4B
aaa-007619
2Y 4 11 4A
5 10
2A 3Y
Transparent top view
6
2B 9 3B
(1) This is not a ground pin. There is no electrical or
GND 7 8 3A
mechanical requirement to solder the pad. In case
aaa-007618
soldered, the solder land should remain floating or
connected to GND.
Fig. 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol Pin Description
1Y, 2Y, 3Y, 4Y 1, 4, 10, 13 data output
1A, 2A, 3A, 4A 2, 5, 8, 11 data input
1B, 2B, 3B, 4B 3, 6, 9, 12 data input
GND 7 ground (0 V)
V 14 supply voltage
CC
74AHC_AHCT02_Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 2 11 May 2020 2 / 12
GND 7 1 1Y
3A 8 14 V
CC