74HC03-Q100 74HCT03-Q100 Quad 2-input NAND gate open-drain output Rev. 3 10 August 2021 Product data sheet 1. General description The 74HC03-Q100 74HCT03-Q100 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC03-Q100: CMOS level For 74HCT03-Q100: TTL level Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC03D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT03D-Q100 74HC03PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package SOT402-1 14 leads body width 4.4 mm 74HCT03PW-Q100Nexperia 74HC03-Q100 74HCT03-Q100 Quad 2-input NAND gate open-drain output 4. Functional diagram 1 3 & 1 1A 2 1Y 3 2 1B 4 4 2A 6 & 2Y 6 5 5 2B Y 9 9 3A 8 3Y 8 & 10 3B 10 A 12 4A 12 4Y 11 11 & 13 4B 13 B GND mna212 aaa-008083 001aab715 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74HC03 74HCT03 74HC03 74HCT03 1 14 1A V CC 1B 2 13 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 1Y 3 12 4A 4 11 2A 4Y 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 6 9 2Y 3A GND 7 8 3Y GND 7 8 3Y aaa-008084 aaa-008085 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74HC HCT03 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 10 August 2021 2 / 11