74LV00 Quad 2-input NAND gate Rev. 5 10 September 2021 Product data sheet 1. General description The 74LV00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 to 5.5 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 C OH CC amb Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV00D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV00PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV00BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LV00 Quad 2-input NAND gate 4. Functional diagram 1 3 & 1 1A 2 1Y 3 2 1B 4 4 2A 6 & 2Y 6 5 5 2B 9 9 3A 3Y 8 8 & 10 3B 10 A 12 4A 12 4Y 11 Y 11 13 4B & 13 B mna212 mna246 mna211 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74LV00 terminal 1 index area 1B 2 13 4B 1Y 3 12 4A 74LV00 2A 4 11 4Y 5 (1) 10 2B 3B V CC 1A 1 14 V CC 2Y 6 9 3A 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 001aah092 2B 5 10 3B Transparent top view 2Y 6 9 3A (1) This is not a supply pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case aaa-033972 soldered, the solder land should remain floating or connected to V CC Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74LV00 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 10 September 2021 2 / 12 GND 7 1 1A 3Y 8 14 V CC