74LV04PW,118

74LV04 Hex inverter Rev. 5 13 September 2021 Product data sheet 1. General description The 74LV04 is a hex inverter. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 to 5.5 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 C OH CC amb Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV04D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV04PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV04BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LV04 Hex inverter 4. Functional diagram 1 1 2 1A 1Y 2 1 1 3 4 3 2A 2Y 4 1 5 6 5 3A 3Y 6 1 9 8 4Y 9 4A 8 1 5Y 11 5A 10 11 10 13 6A 6Y 12 1 13 12 A Y mna342 mna343 mna341 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74LV04 terminal 1 index area 1Y 2 13 6A 3 12 2A 6Y 74LV04 2Y 4 11 5A 3A 5 (1) 10 5Y V CC 1A 1 14 V CC 3Y 6 9 4A 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 001aah094 3A 5 10 5Y Transparent top view 3Y 6 9 4A (1) This is not a supply pin. There is no electrical or GND 7 8 4Y mechanical requirement to solder the pad. In case aaa-033974 soldered, the solder land should remain floating or connected to V CC Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74LV04 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 13 September 2021 2 / 12 GND 7 1 1A 4Y 8 14 V CC