HEF4094BT,653

HEF4094B 8-stage shift-and-store register Rev. 14 8 July 2021 Product data sheet 1. General description The HEF4094B is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . DD 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Wide supply voltage range from 3.0 to 15.0 V CMOS low power dissipation High noise immunity Standardized symmetrical output characteristics ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF R = 0 ) Complies with JEDEC standard JESD 13-B Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information All types operate from -40 C to +125 C. Type number Package Name Description Version HEF4094BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 HEF4094BTT TSSOP16 plastic thin shrink small outline package 16 leads body width 4.4 mm SOT403-1Nexperia HEF4094B 8-stage shift-and-store register 4. Functional diagram 3 1 CP STR QS1 9 QS2 10 QP0 4 D 2 8-STAGE SHIFT QS2 10 QP1 5 CP REGISTER 3 QP2 6 QS1 9 2 D QP3 7 STR 8-BIT STORAGE 1 14 REGISTER QP4 QP5 13 QP6 12 OE 15 3-STATE OUTPUTS QP7 11 OE QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 15 4 5 6 7 14 13 12 11 001aaf119 001aaf111 Fig. 1. Functional diagram Fig. 2. Logic symbol STAGE 0 STAGES 1 TO 6 STAGE 7 D D Q D Q D Q QS1 CP CP D Q QS2 FF 0 FF 7 CP CP LE LATCH D Q D Q LE LE LATCH 0 LATCH 7 STR OE 001aag799 QP0 QP2 QP4 QP6 QP1 QP3 QP5 QP7 Fig. 3. Logic diagram HEF4094B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 14 8 July 2021 2 / 15