HEF4024BT,653 NXP

HEF4024B 7-stage binary counter Rev. 7 18 November 2011 Product data sheet 1. General description The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Tolerant of slow clock rise and fall time Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Frequency dividers Time delay circuits 4. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C Type number Package Name Description Version HEF4024BP DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 HEF4024BT SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1HEF4024B NXP Semiconductors 7-stage binary counter 5. Functional diagram Q6 3 Q5 4 12 Q0 7-STAGE Q4 5 1 11 Q1 CP COUNTER 9 Q3 6 Q2 6 Q3 Q2 9 2 5 Q4 MR Q1 11 4 Q5 3 Q0 12 Q6 001aab906 CP MR 1 2 001aab908 Fig 1. Functional diagram Fig 2. Logic symbol Q Q Q Q Q Q Q FF FF FF FF FF FF FF 1 2 3 4 5 6 7 CP T T T T T T T Q Q Q Q Q Q Q RD RD RD RD RD RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 001aab909 Fig 3. Logic diagram HEF4024B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 18 November 2011 2 of 14