HEF4040BP,652 NXP

HEF4040B 12-stage binary ripple counter Rev. 8 17 November 2011 Product data sheet 1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Tolerant of slow clock rise and fall time Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Frequency dividing circuits Time delay circuits Control counters 4. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF4040BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4040BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4040B NXP Semiconductors 12-stage binary ripple counter 5. Functional diagram 10 CP T 12-STAGE COUNTER 11 MR C D 9 7 6 5 3 2 4 13 12 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad589 Fig 1. Functional diagram FF 1 FF 2 FF 12 Q Q Q CP T T T Q Q Q CD CD CD MR Q0 Q1 Q11 001aae615 Fig 2. Logic diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CP input MR input Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad587 Fig 3. Timing diagram HEF4040B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 17 November 2011 2 of 14