MPC5553MZQ132

Document Number: MPC5553 Freescale Semiconductor Rev. 4, Apr 2012 Data Sheet: Technical Data MPC5553 Microcontroller Data Sheet by: Microcontroller Division Contents This document provides electrical specifications, pin 1 Overview . 1 assignments, and package diagrams for the MPC5553 2 Ordering Information 3 microcontroller device. For functional characteristics, 3 Electrical Characteristics . 4 refer to the MPC5553/MPC5554 Microcontroller 3.1 Maximum Ratings 4 Reference Manual. 3.2 Thermal Characteristics 6 3.3 Package . 9 3.4 EMI (Electromagnetic Interference) Characteristics 9 3.5 ESD (Electromagnetic Static Discharge) Characteris- 1 Overview tics . 10 3.6 Voltage Regulator Controller (VRC) and Power-On The MPC5553 microcontroller (MCU) is a member of Reset (POR) Electrical Specifications 10 the MPC5500 family of microcontrollers built on the 3.7 Power-Up/Down Sequencing 11 3.8 DC Electrical Specifications 15 Power Architecture embedded technology. This family 3.9 Oscillator and FMPLL Electrical Characteristics 21 of parts has many new features coupled with high 3.10 eQADC Electrical Characteristics . 23 performance CMOS technology to provide substantial 3.11 H7Fa Flash Memory Electrical Characteristics . 24 3.12 AC Specifications . 25 reduction of cost per feature and significant performance 3.13 AC Timing . 27 improvement over the MPC500 family. 3.14 Fast Ethernet AC Timing Specifications 46 4 Mechanicals 50 The host processor core of this device complies with the 4.1 MPC5553 208 MAP BGA Pinout 50 Power Architecture embedded category that is 100% 4.2 MPC5553 324 PBGA Pinouts 51 4.3 MPC5553 416 PBGA Pinout . 51 user-mode compatible (including floating point library) 4.4 MPC5553 208-Pin Package Dimensions . 55 with the original PowerPC instruction set. The embedded 4.5 MPC5553 324-Pin Package Dimensions . 57 4.6 MPC5553 416-Pin Package Dimensions . 59 architecture enhancements improve the performance in 5 Revision History for the MPC5553 Data Sheet 61 embedded applications. The core also has additional 5.1 Information Changed Between instructions, including digital signal processing (DSP) Revisions 3.0 and 4.0 . 61 5.2 Information Changed Between instructions, beyond the original PowerPC instruction Revisions 2.0 and 3.0 . 61 set. Freescale Semiconductor, Inc., 2008-2012. All rights reserved.Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5553 has two levels of memory hierarchy. The fastest accesses are to the 8-kilobytes (KB) unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and 1.5-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data. The external bus interface is designed to support most of the standard memories used with the MPC5xx family. The complex input/output timer functions of the MPC5553 are performed by an enhanced time processor unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language. The less complex timer functions of the MPC5553 are performed by the enhanced modular input/output system (eMIOS). The eMIOS 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications interfaces (eSCIs). The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). The 324 and 416 packages have 40-channels. The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule (SIU DISR)provides multiplexing of eQADC trigger sources and external interrupt signal multiplexing. The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps Ethernet/IEEE 802.3 networks and is compatible with three different standard MAC (media access controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or 100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and DMA support. MPC5553 Microcontroller Data Sheet, Rev. 4 2 Freescale Semiconductor