Freescale Semiconductor Document Number: MPC5634M Rev. 8, Feb 2011 Data Sheet: Advance Information MPC5634M 144 LQFP 100 LQFP 20 x 20 mm 14 x 14 mm MPC5634M Microcontroller 176 LQFP 208 MAPBGA Data Sheet 24 x 24 mm 17 x 17 mm Operating Parameters Single issue, 32-bit Power Architecture Book E Fully static operation, 0 MHz 80 MHz (plus 2% compliant CPU frequency modulation - 82 MHz) In-order execution and retirement 40 C to 150 C junction temperature operating range Precise exception handling Low power design Branch processing unit Less than 400 mW power dissipation (nominal) Dedicated branch address calculation adder Designed for dynamic power management of core Branch acceleration using Branch Lookahead and peripherals Instruction Buffer Software controlled clock gating of peripherals Load/store unit One-cycle load latency Low power stop mode, with all clocks stopped Fully pipelined Fabricated in 90 nm process 1.2 V internal logic Big and Little Endian support Single power supply with 5.0 V 5% (4.5 V to Misaligned access support 5.25 V) with internal regulator to provide 3.3 V and Zero load-to-use pipeline bubbles 1.2 V for the core Thirty-two 64-bit general purpose registers (GPRs) Input and output pins with 5.0 V 5% (4.5 V to Memory management unit (MMU) with 16-entry 5.25 V) range fully-associative translation look-aside buffer (TLB) 35%/65% V CMOS switch levels (with DDE Separate instruction bus and load/store bus hysteresis) Vectored interrupt support Selectable hysteresis Interrupt latency < 120 ns 80 MHz (measured from Selectable slew rate control interrupt request to execution of first instruction of Nexus pins powered by 3.3 V supply interrupt exception handler) Designed with EMI reduction techniques Non-maskable interrupt (NMI) input for handling Phase-locked loop external events that must produce an immediate response, e.g., power down detection. On this device, the Frequency modulation of system clock frequency NMI input is connected to the Critical Interrupt Input. On-chip bypass capacitance (May not be recoverable) Selectable slew rate and drive strength Critical Interrupt input. For external interrupt sources High performance e200z335 core processor that are higher priority than provided by the Interrupt 32-bit Power Architecture Book E programmers model Controller. (Always recoverable) Variable Length Encoding Enhancements New Wait for Interrupt instruction, to be used with new Allows Power Architecture instruction set to be low power modes optionally encoded in a mixed 16 and 32-bit Reservation instructions for implementing instructions read-modify-write accesses Results in smaller code size Signal processing extension (SPE) APU This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2008, 20102011. All rights reserved. Table of Contents 1 Introduction 9 4.1 Parameter classification 65 1.1 Document overview .9 4.2 Maximum ratings . 65 1.2 Description .9 4.3 Thermal characteristics 67 2 Overview .10 4.3.1 General notes for specifications at maximum 2.1 Device comparison 11 junction temperature . 69 2.2 MPC5634M features .12 4.4 Electromagnetic Interference (EMI) characteristics . 72 2.3 MPC5634M feature details 19 4.5 Electromagnetic static discharge (ESD) characteristics72 2.3.1 e200z335 core 19 4.6 Power Management Control (PMC) and Power On Reset 2.3.2 Crossbar 20 (POR) electrical specifications . 73 2.3.3 eDMA .21 4.6.1 Regulator example 77 2.3.4 Interrupt controller .21 4.6.2 Recommended power transistors . 77 2.3.5 FMPLL 22 4.7 Power up/down sequencing . 78 2.3.6 Calibration EBI 22 4.8 DC electrical specifications . 79 2.3.7 SIU .23 4.9 I/O Pad current specifications . 86 2.3.8 ECSM 24 4.9.1 I/O pad VRC33 current specifications . 87 2.3.9 Flash .24 4.9.2 LVDS pad specifications 88 2.3.10 SRAM 25 4.10 Oscillator and PLLMRFM electrical characteristics . 89 2.3.11 BAM 25 4.11 Temperature sensor electrical characteristics . 91 2.3.12 eMIOS 25 4.12 eQADC electrical characteristics . 91 2.3.13 eTPU2 26 4.13 Platform flash controller electrical characteristics 94 2.3.14 eQADC .28 4.14 Flash memory electrical characteristics . 94 2.3.15 DSPI .29 4.15 AC specifications . 96 2.3.16 eSCI 31 4.15.1 Pad AC specifications 96 2.3.17 FlexCAN 32 4.16 AC timing . 99 2.3.18 System timers 32 4.16.1 IEEE 1149.1 interface timing 99 2.3.19 Software Watchdog Timer (SWT) .33 4.16.2 Nexus timing 102 2.3.20 Debug features .34 4.16.3 Calibration bus interface timing . 105 2.4 MPC5634M series architecture .36 4.16.4 eMIOS timing . 108 2.4.1 Block diagram 36 4.16.5 DSPI timing 108 2.4.2 Block summary .36 4.16.6 eQADC SSI timing . 114 3 Pinout and signal description .38 5 Packages . 115 3.1 144 LQFP pinout 39 5.1 Package mechanical data . 115 3.2 176 LQFP pinout (MPC5634M) 39 5.1.1 144 LQFP 115 3.3 176 LQFP pinout (MPC5633M) 41 5.1.2 176 LQFP 119 3.4 208 MAPBGA ballmap (MPC5634M) 42 5.1.3 208 MAPBGA . 122 3.5 208 MAPBGA ballmap (MPC5633M only) 43 6 Ordering information 124 3.6 Signal summary 44 7 Document revision history 126 3.7 Signal details .60 4 Electrical characteristics .65 MPC5634M Microcontroller Data Sheet, Rev. 8 2 Freescale Semiconductor