15025-512-XTD ON Semiconductor

FS6377 Programmable 3-PLL Clock Generator IC 1.0 Key Features Three on-chip PLLs with programmable reference and feedback dividers Four independently programmable muxes and post dividers 2 I C-bus serial interface Programmable power-down of all PLLs and output clock drivers One PLL and two mux/post-divider combinations can be modified by SEL CD input Tristate outputs for board testing 5V to 3.3V operation Accepts 5MHz to 27MHz crystal resonators Commercial and industrial temperature ranges offered 2.0 General Description The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three 2 I C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility. Figure 1: Pin Configuration 2008 SCILLC. All rights reserved. Publication Order Number: May 2008 Rev. 4 FS6377/D FS6377 Figure 2: Block Diagram Table 1: Pin Descriptions Pin Type Name Description U 1 DI O SDA Serial interface data input/output U 2 DI SEL CD Selects one of two PLL C, mux D/C and post divider C/D combinations U 3 DI PD Power-down input 4 P VSS Ground 5 AI XIN Crystal oscillator input 6 AO XOUT Crystal oscillator output U 7 DI OE Output enable input 8 P VDD Power supply (5V to 3.3V) U 9 DI ADDR Address select 10 DO CLK D D clock output 11 P VSS Ground 12 DO CLK C C clock output 13 DO CLK B B clock output 14 P VDD Power supply (5V to 3.3V) 15 DO CLK A A clock output U 16 DI SCL Serial interface clock output U D Key: AI: Analog Input AO = Analog Output DI = Digital Input DI = Input with Internal Pull-up DI = Input with Internal Pull-down DIO = Digital Input/Output DI-3 = Three-level Digital Input DO = Digital Output P = Power/Ground = Active Low Pin Rev. 4 Page 2 of 24 www.onsemi.com