DATA SHEET www.onsemi.com Single 2 A High-Speed, Low-Side Gate Driver WDFN6 2x2, 065P SOT235 CASE 527AH CASE 511CY FAN3100T, FAN3100C Description The FAN3100 2 A gate driver is designed to drive an Nchannel PIN ASSIGNMENT enhancementmode MOSFET in lowside switching applications by providing high peak current pulses during the short switching IN+ 1 6 IN intervals. The driver is available with either TTL (FAN3100T) or CMOS (FAN3100C) input thresholds. Internal circuitry provides AGND 2 5 PGND an undervoltage lockout function by holding the output LOW until the supply voltage is within the operating range. The FAN3100 VDD 3 4 OUT delivers fast MOSFET switching performance, which helps maximize efficiency in highfrequency power converter designs. 6Lead MLP (Top View) FAN3100 drivers incorporate MillerDrive architecture forthefinal output stage. This bipolar MOSFET combination 1 5 VDD OUT provides high peak current during the Miller plateau stage of the MOSFET turnon / turnoff process to minimize switching loss, while providing railtorail voltage swing and reverse current GND 2 capability. The FAN3100 also offers dual inputs that can be configured IN+ 3 4 IN to operate in non inverting or inverting mode and allow implementation of an enable function. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is SOT235 (Top View) pulled LOW to hold the power MOSFET off. The FAN3100 is available in a leadfree finish, 2x2 mm, 6lead, Molded Leadless Package (MLP) for the smallest size with excellent MARKING DIAGRAM thermal performance or industrystandard, 5pin, SOT23. Features 3 A Peak Sink/Source at V = 12 V DD &E&E&Y &O100X&C 4.5 to 18 V Operating Range &.&O&E&V 2.5 A Sink/1.8 A Source at V = 6 V OUT DualLogic Inputs Allow Configuration as NonInverting or Inverting with Enable Function &E = Designates Space Internal Resistors Turn Driver Off If No Inputs &Y = Binary Calendar Year Coding Scheme &O = Plant Code identifier 13 ns Typical Rise Time and 9 ns Typical FallTime with 1 nF Load 100X = Device Specific Code Choice of TTL or CMOS Input Thresholds X = T or C &C = Single digit Die Run Code MillerDrive Technology &. = Pin One Dot Typical Propagation Delay Time Under 20 ns with Input Falling or &V = EightWeek Binary Datecoding Scheme Rising 6Lead, 2x2 mm MLP or 5Pin, SOT23 Packages Rated from 40C to 125C Ambient ORDERING INFORMATION These Devices are PbFree and Halogen Free See detailed ordering and shipping information on page 17 of this data sheet. Applications SwitchMode Power Supplies (SMPS) HighEfficiency MOSFET Switching Synchronous Rectifier Circuits DCtoDC Converters Semiconductor Components Industries, LLC, 2007 1 Publication Order Number: August, 2021 Rev. 4 FAN3100T/DFAN3100T, FAN3100C Motor Control BLOCK DIAGRAMS THERMAL CHARACTERISTICS (Note 1) JL JT JA JB JT (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Package Unit 6Lead, 2x2 mm Molded Leadless Package (MLP) 2.7 133 58 2.8 42 C/W SOT23, 5Lead 56 99 157 51 5 C/W 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the MLP6 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOT235 package, the board reference is defined as the PCB copper adjacent to pin 2. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. PIN DEFINITIONS SOT23 Pin MLP Pin Number Number Name Description 1 3 VDD Supply Voltage. Provides power to the IC. 2 AGND Analog ground for input signals (MLP only). Connect to PGND underneath the IC. 2 GND Ground (SOT23 only). Common ground reference for input and output circuits. 3 IN+ NonInverting Input. Connect to VDD to enable output. 1 4 6 IN Inverting Input. Connect to AGND or PGND to enable output. 5 4 OUT Gate Drive Output: Held LOW unless required inputs are present and V is above DD UVLO threshold. Pad P1 Thermal Pad (MLP only). Exposed metal on the bottom of the package, which is electrically connected to pin 5. 5 PGND Power Ground (MLP only). For output drive circuit separates switching noise from inputs. OUTPUT LOGIC IN+ IN OUT 0 (Note 7) 0 0 0 (Note 7) 1 (Note 7) 0 1 0 1 1 1 (Note 7) 0 7. Default input signal if no external connection is made. www.onsemi.com 2