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The switch node has been internally DS(on) GS D connected to enable easy placement and routing of synchronous Max r = 11 m at V = 4.5 V, I = 11 A DS(on) GS D buck converters. The control MOSFET (Q1) and synchronous Q2: N-Channel TM SyncFET (Q2) have been designed to provide optimal power Max r = 1.8 m at V = 10 V, I = 30 A DS(on) GS D efficiency. Max r = 2.2 m at V = 4.5 V, I = 27 A DS(on) GS D Applications Low inductance packaging shortens rise/fall times, resulting in lower switching losses Computing MOSFET integration enables optimum layout for Communications lower circuit inductance and reduced switch node General Purpose Point of Load ringing Notebook VCORE RoHS Compliant G1 Pin 1 D1 Pin 1 D1 D1 Q 2 S2 D1 5 4 D1 PHASE PHASE D1 S2 6 3 (S1/D2) S2 D1 7 2 G2 S2 G2 S2 G1 8 1 Q 1 S2 Top Power 56 Bottom MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 30 30 V DS V Gate to Source Voltage (Note 3) 20 12 V GS Drain Current -Continuous (Package limited) T = 25 C 30 60 C -Continuous (Silicon limited) T = 25 C 60 145 C I A D 1a 1b -Continuous T = 25 C 13 30 A -Pulsed 40 120 4 5 E Single Pulse Avalanche Energy 33 86 mJ AS 1a 1b Power Dissipation for Single Operation T = 25 C 2.2 2.5 A P W D 1c 1d Power Dissipation for Single Operation T = 25 C 1 1 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics 1a 1b R Thermal Resistance, Junction to Ambient 57 50 JA 1c 1d R Thermal Resistance, Junction to Ambient 125 120 C/W JA R Thermal Resistance, Junction to Case 2.9 2.2 JC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity 22CF FDMS3660S Power 56 13 12 mm 3000 units 07OD 1 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMS3660S Rev.C4