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FDMS7602S Dual N-Channel PowerTrench MOSFET May 2014 FDMS7602S Dual N-Channel PowerTrench MOSFET Q1: 30 V, 30 A, 7.5 m Q2: 30 V, 30 A, 5.0 m Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a dual MLP package.The switch node has been internally Max r = 7.5 m at V = 10 V, I = 12 A DS(on) GS D connected to enable easy placement and routing of synchronous Max r = 12 m at V = 4.5 V, I = 10 A DS(on) GS D buck converters. The control MOSFET (Q1) and synchronous Q2: N-Channel TM SyncFET (Q2) have been designed to provide optimal power Max r = 5.0 m at V = 10 V, I = 17 A DS(on) GS D efficiency. Max r = 6.8 m at V = 4.5 V, I = 14 A DS(on) GS D Applications RoHS Compliant Computing Communications General Purpose Point of Load Notebook VCORE S2 S2 Q 2 S2 S2 D1 5 4 G2 S1/D2 D1 S2 6 3 D1 D1 S2 D1 7 2 D1 D1 G1 G2 G1 8 1 Q 1 Top Bottom Power 56 MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 30 30 V DS V Gate to Source Voltage (Note 3) 20 20 V GS Drain Current -Continuous T = 25 C 30 30 C 1a 1b I -Continuous T = 25 C 12 17 A D A -Pulsed 40 60 1a 1b Power Dissipation for Single Operation T = 25 C 2.2 2.5 A P W D 1c 1d Power Dissipation for Single Operation T = 25 C 1.0 1.0 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics 1a 1b R Thermal Resistance, Junction to Ambient 57 50 JA 1c 1d R Thermal Resistance, Junction to Ambient 125 120 C/W JA R Thermal Resistance, Junction to Case 3.5 2 JC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDMS7602S FDMS7602S Power 56 13 12 mm 3000 units 1 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMS7602S Rev.C2