MC100LVEL38
3.3VECL 2, 4/6 Clock
Generation Chip
Description
The MC100LVEL38 is a low skew 2, 4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
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internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended input signal.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on the
SOIC20 WB
internal clock when the device is enabled/disabled as can happen with an
DW SUFFIX
asynchronous control. An internal runt pulse could lead to losing
CASE 751D
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
MARKING DIAGRAM*
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
20
the 2 and the 4/6 outputs are both transitioning from a LOW to
aHIGH. This output allows for clock synchronization within the
100LVEL38
system.
AWLYYWWG
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
1
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
A = Assembly Location
design ensures synchronization between the 2 and the 4/6 outputs of
WL = Wafer Lot
a single device. YY = Year
WW = Work Week
The V pin, an internally generated voltage supply, is available to
BB
G = Pb-Free Package
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB *For additional marking information, refer to
Application Note AND8002/D.
V may also rebias AC coupled inputs. When used, decouple V
BB BB
and V via a 0.01F capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
Features
ORDERING INFORMATION
50 ps Maximum Output-to-Output Skew
See detailed ordering and shipping information on page 6 of
this data sheet.
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: > 2 kV Human Body Model Moisture Sensitivity: Level 3 (Pb-Free)
For Additional Information, see Application Note
The 100 Series Contains Temperature Compensation
AND8003/D
PECL Mode Operating Range:
Flammability Rating: UL 94 V0 @ 0.125 in,
V = 3.0 V to 3.8 V with V = 0 V
CC EE
Oxygen Index: 28 to 34
NECL Mode Operating Range:
Transistor Count = 388 devices
V = 0 V with V = 3.0 V to 3.8 V
CC EE
These Devices are Pb-Free, Halogen Free and are
Internal Input 75 k Pulldown Resistors
RoHS Compliant
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 11 MC100LVEL38/DMC100LVEL38
V Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V
CC EE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 678 9 10
V EN DIV_SEL CLK CLK V MR V Phase_Out Phase_Out
CC BB CC
Figure 1. Pinout: 20-Lead SOIC (Top View)
Warning: All V and V pins must be externally connected
CC EE
to Power Supply to guarantee proper operation.
Q0
CLK 2
Q0
R
CLK
Q1
Q1
Q2
EN
R
4/6
Q2
R
Q3
MR
Q3
DIVSEL
PHASE_OUT
Phase
Out
PHASE_OUT
Logic
R
V
BB
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION Table 2. FUNCTION TABLE
Pin Function CLK EN MR Function
CLK, CLK ECL Diff Clock Inputs Z L L Divide
ZZ H L Hold Q
0 3
Q , Q Q , Q ECL Diff 2 Outputs
0 1; 0 1
X X H Reset Q
0 3
Q , Q Q , Q ECL Diff 4/6 Outputs
2 3; 2 3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
EN ECL Sync Enable Input
X = Dont Care
MR ECL Master Reset Input
DIVSEL ECL Frequency Select Input
DVSEL Q , Q OUTPUTS
2 3
Phase_Out, Phase_Out ECL Phase Sync Diff. Signal Output
L Divide by 4
H Divide by 6
V Reference Voltage Output
BB
V Positive Supply
CC
V Negative Supply
EE
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