3.3 VECL Differential Clock D FlipFlop MC100LVEL51 Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from www.onsemi.com a3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3 V V . CC 8 8 The reset input is an asynchronous, level triggered signal. Data enters 1 1 the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of TSSOP8 SOIC8 NB the clock. The differential clock inputs of the LVEL51 allow the device to DT SUFFIX D SUFFIX CASE 948R be used as a negative edge triggered flip-flop. CASE 751 The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V and the CLK input will be biased at V /2. EE CC MARKING DIAGRAMS* Features 8 8 475 ps Propagation Delay KVL51 KV51 ALYW ALYW 2.8 GHz Toggle Frequency ESD Protection: > 4 kV Human Body Model, 1 1 > 200 V Machine Model SOIC8 TSSOP8 The 100 Series Contains Temperature Compensation A = Assembly Location PECL Mode Operating Range: V = 3.0 V to 3.8 V CC L = Wafer Lot with V = 0 V EE Y = Year NECL Mode Operating Range: V = 0 V CC W = Work Week = Pb-Free Package with V = 3.0 V to 3.8 V EE Internal Input Pulldown Resistors (Note: Microdot may be in either location) Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test *For additional marking information, refer to Application Note AND8002/D. Moisture Sensitivity Level Level 1 for SOIC8 NB ORDERING INFORMATION Level 3 for TSSOP8 For Additional Information, see Application Note AND8003/D Device Package Shipping Flammability Rating: UL 94 V0 0.125 in, MC100LVEL51DG SOIC8 NB 98 Units/Tube Oxygen Index: 28 to 34 (Pb-Free) Transistor Count = 114 devices MC100LVEL51DTR2G TSSOP8 2500 / (Pb-Free) Tape & Reel These Devices are Pb-Free, Halogen Free and are RoHS Compliant For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 8 MC100LVEL51/DMC100LVEL51 R 1 8 V CC R D 2 D 7 Q Flip-Flop CLK 3 6 Q CLK45 V EE Figure 1. Logic Diagram and Pinout Assignment Table 2. TRUTH TABLE Table 1. PIN DESCRIPTION PIN FUNCTION D R CLK Q CLK, CLK ECL Differential Clock Input L L Z L H L Z H Q, Q ECL Differential Output X H X L D ECL D Input R ECL Reset Input Z = LOW to HIGH Transition X = Dont Care V Positive Supp y CC V Negative Supply EE Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 NB 190 C/W JA 500 lfpm 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 5% C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board 2S2P (2 signal, 2 power). www.onsemi.com 2