MC74AC652, MC74ACT652 Octal Transceiver/Register with 3-State Outputs (Non-Inverting) The MC74AC/ACT652 consists of registered bus transceiver circuits, with outputs, Dtype flipflops and control circuitry www.onsemi.com providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be MARKING DIAGRAMS loaded into the respective registers on the LOWtoHIGH transition of the appropriate clock pin (CAB or CBA). The four fundamental AC652 data handling functions available are illustrated in Figures 1 to 4. AWLYYWWG 24 Features 1 SO24 ACT652 Independent Registers for A and B Buses DW SUFFIX AWLYYWWG Multiplexed RealTime and Stored Data Transfers CASE 751E Choice of True and Inverting Data Paths A = Assembly Location 3State Outputs WL = Wafer Lot 300 mil Slim DualinLine Package YY = Year Outputs Source/Sink 24 mA WW = Work Week G = PbFree Package ACT652 Has TTL Compatible Inputs These are PbFree Devices ORDERING INFORMATION REAL TIME TRANSFER REAL TIME TRANSFER See detailed ordering and shipping information in the package ABUS TO BBUS BBUS TO ABUS dimensions section on page 9 of this data sheet. ABUS ABUS REG REG REG REG BBUS BBUS Figure 1. Figure 2. STORAGE TRANSFER FROM BUS TO REGISTER FROM REGISTER TO BUS ABUS ABUS REG REG REG REG BBUS BBUS Figure 3. Figure 4. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: March, 2015 Rev. 7 MC74AC652/DMC74AC652, MC74ACT652 V CBA SBA GBA B B B B B B B B CC 0 1 2 3 4 5 6 7 PIN ASSIGNMENT 24 23 22 21 20 19 18 17 16 15 14 13 PIN FUNCTION A A Data Register A Inputs 0 7 Data Register A Outputs B B Data Register B Inputs 0 7 Data Register B Outputs CAB, CBA Clock Pulse Inputs 1 2 3456 7 8 9 10 11 12 SAB, SBA Transmit/Receive Inputs CAB SAB GAB A A A A A A A A GND 0 1 2 3 4 5 6 7 GAB, GBA Output Enable Inputs Figure 5. Pinout: 24Lead Plastic Package (Top View) B B B B B B B B CAB 0 1 2 3 4 5 6 7 SAB GAB CBA SBA GBA A A A A A A A A 0 1 2 3 4 5 6 7 Figure 6. Logic Symbol GBA GAB CBA SBA CAB SAB 1 OF 8 CHANNELS D 0 C 0 B 0 A 0 D 0 C 0 TO 7 OTHER CHANNELS NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 7. Logic Diagram www.onsemi.com 2