NB100LVEP221 2.5V/3.3V2:1:20 Differential HSTL/ECL/PECL Clock Driver Description The NB100LVEP221 is a low skew 2:1:20 differential clock driver, www.onsemi.com designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential MARKING ECL/PECL CLK1/CLK1 can also receive HSTL signal levels. The DIAGRAM* LVPECL input signals can be either differential configuration or 52 singleended (if the V output is used). BB 1 The LVEP221 specifically guarantees low outputtooutput skew. NB100 Optimal design, layout, and processing minimize skew within a device LVEP221 152 and from device to device. AWLYYWWG To ensure tightest skew, both sides of differential outputs should be QFN52 MN SUFFIX terminated identically into 50 even if only one output is being used. CASE 485M If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. A = Assembly Location The NB100LVEP221, as with most other ECL devices, can be WL = Wafer Lot YY = Year operated from a positive V supply in LVPECL mode. This allows the CC WW = Work Week LVEP221 to be used for high performance clock distribution in +3.3 V or G = PbFree Package +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power *For additional marking information, refer to supplies. For more information on PECL terminations, designers should Application Note AND8002/D. refer to Application Note AND8020/D. The V pin, an internally generated voltage supply, is available to this BB device only. For singleended LVPECL input conditions, the unused ORDERING INFORMATION differential input is connected to V as a switching reference voltage. BB See detailed ordering and shipping information in the package V may also rebias AC coupled inputs. When used, decouple V and BB BB dimensions section on page 8 of this data sheet. V via a 0.01 F capacitor and limit current sourcing or sinking to CC 0.5 mA. When not used, V should be left open. BB Singleended CLK input operation is limited to a V 3.0 V in CC LVPECL mode, or V 3.0 V in NECL mode. EE Features 15 ps Typical OutputtoOutput Skew 40 ps Typical DevicetoDevice Skew Jitter Less than 2 ps RMS Maximum Frequency > 1.0 GHz Typical Thermally Enhanced 52Lead QFN Package V Output BB 540 ps Typical Propagation Delay LVPECL and HSTL Mode Operating Range: V = 2.375 V to 3.8 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 2.375 V to 3.8 V CC EE Q Output will Default Low with Inputs Open or at V EE Pin Compatible with Motorola MC100EP221 These Devices are PbFree and are RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: January, 2019 Rev. 11 NB100LVEP221/DNB100LVEP221 Exposed Pad (EP) 39 VCC0 1 Q6 Q6 VCC 2 38 CLKSEL 3 37 Q7 Q7 CLK0 4 36 CLK0 5 35 Q8 VBB 6 34 Q8 CLK1 7 NB100LVEP221 33 Q9 CLK1 8 32 Q9 9 VEE 31 Q10 Q19 10 30 Q10 Q19 11 29 Q11 12 Q18 28 Q11 13 27 VCC0 Q18 Figure 1. 52 Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION CLK0*, CLK0** ECL/PECL Differential Inputs CLK0 CLK1*, CLK1** ECL/PECL or HSTL Differential Inputs 0 Q0:19, Q0:19 ECL/PECL Differential Outputs CLK0 20 Q0 Q19 CLK SEL* ECL/PECL Active Clock Select Input Q0 Q19 V BB CLK1 Reference Voltage Output 20 1 V /V Positive Supply CC CCO CLK1 V EE*** Negative Supply V BB * Pins will default LOW when left open. CLK SEL ** Pins will default HIGH when left open. ***The thermally conductive exposed pad on the bottom of the package is electrically connected to V internally. V EE CC Table 2. FUNCTION TABLE V EE CLK SEL Active Input L CLK0, CLK0 Figure 2. Logic Diagram H CLK1, CLK1 www.onsemi.com 2 VCC0 52 14 Q 0 Q17 15 51 Q0 Q17 16 50 Q1 Q16 49 17 Q1 Q16 18 48 Q2 Q15 19 47 Q2 Q15 46 20 Q 3 Q14 21 45 Q3 Q14 22 44 Q4 Q13 23 43 Q4 Q13 24 42 Q5 Q12 25 41 Q5 Q12 VCC0 26 40