NB3N51044 3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements. The device www.onsemi.com accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four MARKING DIAGRAM differential HCSL/LVDS outputs (See Figure 10 for LVDS interface) of 100 MHz or 125 MHz clock frequency based on frequency select input F SEL. NB3N51044 is configurable to bypass the PLL from NB3N5 signal path using BYPASS, and provides the output frequency through 1044G the divider network. All clock outputs can be individually enabled / ALYW TSSOP28 disabled through hardware input pins OE 3:0 . In addition, device can DT SUFFIX be reset using Master Reset input pin MR OE . CASE 948AA Features A = Assembly Location L = Wafer Lot Uses 25 MHz Fundamental Crystal or Reference Clock Input Y = Year Four Low Skew HCSL or LVDS Outputs W = Work Week Output Frequency Selection of 100 MHz or 125 MHz G = PbFree Package Individual OE TriStates Outputs Master Reset and BYPASS Modes ORDERING INFORMATION See detailed ordering and shipping information on page 12 of PCIe Gen 1, Gen 2, Gen 3, Gen 4 Compliant this data sheet. Typical Phase Jitter 125 MHz (Integrated 1.875 MHz to 20 MHz): 0.2 ps Typical CycleCycle Jitter 100 MHz (10k cycles): 20 ps Phase Noise 100 MHz: Offset Noise Power 100 Hz 101 dBc/Hz 1 kHz 123 dBc/Hz 10 kHz 133 dBc/Hz 100 kHz 136 dBc/Hz 1 MHz 141 dBc/Hz 10 MHz 155 dBc/Hz Operating Supply Voltage Range 3.3 V 5% Industrial Temperature Range 40C to +85C Functionally Compatible with ICS841604I with enhanced performance These are PbFree Devices Applications End Products Networking Switch and Router Consumer Set Top Box, LCD TV Computing and Peripherals Servers, Desktop Computers Industrial Equipment Automated Test Equipment PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4 Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: September, 2017 Rev. 2 NB3N51044/DNB3N51044 BLOCK DIAGRAM V BYPASS MR OE DD CLK3 HCSL buffer CLK3 OE3 CLK2 HCSL XIN buffer CLK2 0 25 MHz Output Crystal Clock Buffer/ Charge Phase Divider OE2 1 Cystal Oscillator Pump VCO Detector ( N) XOUT CLK1 HCSL buffer CLK1 REF IN Feedback OE1 Divider CLK0 HCSL CLK0 buffer OE0 GND REF SEL F SEL IREF Figure 1. Block Diagram PIN CONFIGURATION 1 28 V REF SEL DD REF IN 2 27 BYPASS V 3 26 IREF DD F SEL GND 4 25 V 5 24 XIN DD 6 23 CLK3 XOUT CLK3 MR OE 7 NB3N51044 22 CLK2 V 21 DD 8 OE3 9 20 CLK2 GND 10 19 OE2 CLK1 OE1 11 18 CLK1 OE0 17 12 GND CLK0 13 16 V CLK0 DD 14 15 Figure 2. Pin Configuration (Top View) www.onsemi.com 2