P2781/82/84
General Purpose EMI
Reduction IC
Features source, which provides system wide reduction of EMI of all
clock dependent signals. The P278xA allows significant
Provides up to 15dB of EMI suppression
system cost savings by reducing the number of circuit
FCC approved method of EMI attenuation
board layers and shielding that are traditionally required to
Generates a 1X, 2X, and 4X low EMI spread spectrum
pass EMI regulations.
clock of the input frequency
Input frequency range from 3 to 78MHz
The P278xA uses the most efficient and optimized
modulation profile approved by the FCC. The P278xA
External loop filter for spread % adjustment
modulates the output of a single PLL in order to spread
Spreading ranges from 0.25% to 5.0%
the bandwidth of a synthesized clock and, more
Ultra low cycle-to-cycle jitter
importantly, decreases the peak amplitudes of its
Zero-cycle slip
harmonics. This result in significantly lower system EMI
3.3V operating voltage range
compared to the typical narrow band signal produced by
Ultra-low power CMOS design
oscillators and most frequency generators. Lowering EMI
P278xA is available in an 8 pin SOIC Package
by increasing a signals bandwidth is called spread
spectrum clock generation.
Product Description
The P278xA is a versatile spread spectrum frequency
Applications
modulator designed specifically for digital camera and other
The P278xA is targeted towards MFP, xDSL, fax modem,
digital video and imaging applications. The P278xA
set-top box, USB controller, DSC, and embedded systems.
reduces electromagnetic interference (EMI) at the clock
Block Diagram
FS0 FS1
LF
VDD
PLL
Modulation
XIN / CLKIN
Frequency
Crystal
Divider
Output
Oscillator
Phase VCO
XOUT
Divider
Detector
Feedback
Divider
ModOUT
VSS
2010 SCILLC. All rights reserved. Publication Order Number:
NOVEMBER 2010 Rev. 2.1 P2781/82/84 P2781/82/84
Pin Configuration
XIN / CLKIN 1 8
VDD
XOUT
2 7 FS0
P278xA
3 6 ModOUT
FS1
VSS
4 5
LF
Standard pin Configuration offered in both
8 pin SOIC Packages.
Pin Description (P278xA)
Pin# Pin Name Type Description
Connect to crystal or clock input. This pin has dual functions. It can be connected
1 XIN/CLKIN I
either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left
2 XOUT O
unconnected.
Digital logic input used to select input frequency range (see the Input Frequency
3 FS1 I
Selection Table). This pin has an internal pull-up resistor.
External Loop Filter for the PLL. By changing the value of the CRC circuit, the
4 LF I percentage spread can be adjusted accordingly. See the Loop Filter Selection
Table for detail value.
5 VSS I Ground Connection. Connect to system ground.
6 ModOUT O Spread Spectrum Clock Output.
Digital logic input used to select input frequency range (see the Input Frequency
7 FS0 I
Selection Table). This pin has an internal pull-up resistor.
8 VDD P Connect to +3.3 V
Input Frequency Selection Table
Output Frequency Scaling (MHz)
FS1 FS0 Input (MHz) Modulation Rate (KHz)
P2781A P2782A P2784A
0 0 3 to 9 3 to 9 6 to 18 12 to 36 Fin / 128
0 1 10 to 19 10 to 19 20 to 38 40 to 76 Fin / 256
1 0 20 to 38 20 to 38 40 to 76 80 to 152 Fin / 512
1 1 39 to 78 39 to 78 78 to 156 156 to 312 Fin / 1024
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