P3P623S00B,
P3P623S00E
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Timing-Safe Peak EMI
Reduction IC
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Functional Description
P3P623S00B/E is a versatile, 3.3 V Zerodelay buffer designed to
distribute TimingSafe clocks with Peak EMI reduction. P3P623S00B
is an eightpin version, accepts one reference input and drives out one 8
lowskew TimingSafe clock. P3P623S00E accepts one reference
1
input and drives out eight lowskew TimingSafe clocks.
SOIC8 NB TSSOP16
P3P623S00B/E has an SS% that selects 2 different Deviation and
CASE 751 CASE 948AN
associated InputOutput Skew (T ). Refer to the Spread
SKEW
Spectrum Control and InputOutput Skew table for details.
P3P623S00E has a CLKOUT for adjusting the InputOutput clock
delay, depending upon the value of capacitor connected at this pin to
GND.
PIN CONFIGURATION
P3P623S00B/E operates from a 3.3 V supply and is available in two
different packages, as shown in the ordering information table.
CLKIN 1 8
Application NC
P3P623S00B/E is targeted for use in Displays and memory interface
NC 2
7
VDD
systems.
P3P623S00B
General Features 3 6
SS%
CLKOUT
Clock Distribution with TimingSafe Peak EMI Reduction
4 5
GND
SSON
Input Frequency Range: 20 MHz 50 MHz
2 Different Spread Selection Options
Spread Spectrum can be Turned ON/OFF
External InputOutput Delay Control Option
16
CLKIN 1 CLKOUT
Supply Voltage: 3.3 V 0.3 V
P3P623S00B: 8 Pin SOIC 2 CLKOUT7
CLKOUT1 15
P3P623S00E: 16 Pin TSSOP
3 14 CLKOUT6
VDD
The First True Dropin Solution
13
SS% 4 VDD
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
P3P623S00E
Compliant
GND 5 12
GND
CLKOUT2 6
11 CLKOUT5
10
7 CLKOUT4
CLKOUT3
8 9
DLY_CTRL SSON
This document contains information on a product under development. ON Semiconductor
ORDERING INFORMATION
reserves the right to change or discontinue this product without notice.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
February, 2015 Rev. P3 P3P623S00/DP3P623S00B, P3P623S00E
VDD
DLY_CTRL
SS%
CLKIN
PLL
CLKOUT(s)*
(TimingSafe)
*For P3P623S00E 8 CLKOUTS
SSON
GND
Figure 1. General Block Diagram
Spread Spectrum Frequency Generation
center modulation, the average frequency is the same as the
The clocks in digital systems are typically square waves
unmodulated frequency and there is no performance
with a 50% duty cycle and as frequencies increase the edge
degradation.
rates also get faster. Analysis shows that a square wave is
Zero Delay and Skew Control
composed of fundamental frequency and harmonics. The
All outputs should be uniformly loaded to achieve Zero
fundamental frequency and harmonics generate the energy
Delay between input and output. Since the CLKOUT pin is
peaks that become the source of EMI. Regulatory agencies
the internal feedback to the PLL, its relative loading can
test electronic equipment by measuring the amount of peak
adjust the inputoutput delay.
energy radiated from the equipment. In fact, the peak level
For applications requiring zero inputoutput delay, all
allowed decreases as the frequency increases. The standard
outputs, including CLKOUT, must be equally loaded. Even
methods of reducing EMI are to use shielding, filtering,
if CLKOUT is not used, it must have a capacitive load equal
multilayer PCBs, etc. These methods are expensive.
to that on other outputs, for obtaining zero inputoutput
Spread spectrum clocking reduces the peak energy by
delay.
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The P3P623S00B/E uses
TimingSafe Technology
the center modulation spread spectrum technique in which
TimingSafe technology is the ability to modulate a clock
the modulated output frequency varies above and below the
source with Spread Spectrum technology and maintain
reference frequency with a specified modulation rate. With
synchronization with any associated data path.
Table 1. PIN DESCRIPTION FOR P3P623S00B
Pin # Pin Name Type Description
1 CLKIN (Note 1) Input External reference Clock input, 5 V tolerant input
2 NC No Connect
3 SS% (Note 3) Input Spread Spectrum Selection. Has an internal pull up resistor
4 GND Power Ground
5 SSON (Note 3) Input Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum is
enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor
6 CLKOUT (Note 2) Output Buffered clock output (Note 4)
7 VDD Power 3.3 V supply
8 NC No Connect
1. Weak pull down
2. Weak pulldown on all outputs
3. Weak pullup on these inputs
4. Buffered clock output is TimingSafe
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