Product Specification PE43701 50 RF Digital Attenuator 7-bit, 31.75 dB, 9 kHz - 4.0 GHz Product Description Features The PE43701 is a HaRP-enhanced, high linearity, 7-bit RF Digital Step Attenuator (DSA). This highly versatile DSA HaRP-enhanced UltraCMOS device covers a 31.75 dB attenuation range in 0.25 dB steps. The Attenuation: 0.25 dB steps to 31.75 dB Peregrine 50 RF DSA provides a parallel or serial- addressable CMOS control interface. It maintains high High Linearity: Typical +59 dBm IIP3 attenuation accuracy over frequency and temperature and Excellent low-frequency performance exhibits very low insertion loss and low power consumption. 3.3 V or 5.0 V Power Supply Voltage Performance does not change with V due to on-board DD regulator. This next generation Peregrine DSA is available in a Fast switch settling time 5x5 mm 32-lead QFN footprint. Programming Modes: Direct Parallel The PE43701 is manufactured on Peregrines UltraCMOS Latched Parallel process, a patented variation of silicon-on-insulator (SOI) Serial-Addressable: Program up to technology on a sapphire substrate, offering the performance eight addresses 000 - 111 of GaAs with the economy and integration of conventional High-attenuation state power-up (PUP) CMOS. CMOS Compatible Figure 1. Package Type No DC blocking capacitors required 32-lead 5x5x0.85 mm QFN Package Packaged in a 32-lead 5x5x0.85 mm QFN Figure 2. Functional Schematic Diagram Switched Attenuator Array RF Output RF Input Parallel Control 7 Serial In Control Logic Interface CLK LE A0 A1 A2 P/S Document No. 70-0243-06 www.psemi.com 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE43701 Product Specification Table 1. Electrical Specifications +25C, V = 3.3 V or 5.0 V DD Parameter Test Conditions Frequency Min Typical Max Units Frequency Range 9 kHz 4.0 GHz Attenuation Range 0.25 dB Step 0 31.75 dB Insertion Loss 9 kHz 4 GHz 1.9 2.4 dB 0 dB - 7.75 dB Attenuation settings 9 kHz < 3 GHz (0.2+1.5%) dB Attenuation Error 8 dB - 31.75 dB Attenuation settings 9 kHz < 3 GHz (0.15+4%) dB (0.25+4.5%) 0 dB - 31.75 dB Attenuation settings 3 GHz 4 GHz dB Return Loss 9 kHz - 4 GHz 18 dB Relative Phase All States 9 kHz - 4 GHz 44 deg P1dB (note 1) Input 20 MHz - 4 GHz 30 32 dBm IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 4 GHz 59 dBm Typical Spurious Value 1MHz -110 dBm Video Feed Through 10 mVpp Switching Time 50% DC CTRL to 10% / 90% RF 650 ns RF Trise/Tfall 10% / 90% RF 400 ns RF settled to within 0.05 dB of final value Settling Time 4 25 s RBW = 5 MHz, Averaging ON. Note 1. Please note Maximum Operating Pin (50 ) of +23dBm as shown in Table 3. Performance Plots Figure 3. 0.25 dB Step Error vs. Frequency* Figure 4. 0.25dB Attenuation vs. Attenuation State 200 MHz 900 MHz 1800 MHz 0.25-dB PE43701 Attenuation 2200 MHz 3000 MHz 0.50 35 900 MHz 1800 MHz 30 2200 MHz 3800 MHz 25 0.25 20 15 0.00 10 5 -0.25 0 0 4 8 12 162024 2832 03510 15 20 25 305 Attenuation Setting (dB) Attenuation State *Monotonicity is held so long as Step-Error does not cross below -0.25 Figure 5. 0.25 dB Major State Bit Error Figure 6. 0.25 dB Attenuation Error vs. Frequency 0.25dB State 0.5dB State 1dB State 2dB State 4dB State 8dB State 200 MHz 900 MHz 1800 MHz 16dB State 31.75dB State 2200 MHZ 3000 MHz 4000 MHz 1.5 1.5 1.0 1.0 0.5 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 0 1000 2000 3000 4000 Attenuation Setting (dB) Frequency (MHz) 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 UltraCMOS RFIC Solutions Page 2 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: