DATASHEET LOCO PLL CLOCK GENERATOR ICS514 Description Features TM The ICS514 LOCO is the most cost effective way to Packaged as 8-pin SOIC or die generate a high-quality, high-frequency clock output Pb (lead) free package from a 14.31818 MHz crystal or clock input. The name IDTs lowest cost PLL clock plus reference LOCO stands for Low Cost Oscillator, as it is designed Produces common computer frequencies to replace crystal oscillators in most electronic Input crystal frequency typically 14.3182 MHz systems. Using Phase-Locked Loop (PLL) techniques, Output clock frequencies up to 66.66 MHz from a the device uses a standard, inexpensive crystal to 14.3182 MHz crystal or input clock produce output clocks up to 66.66 MHz. Low jitter of 50 ps (one sigma) Stored in the chips ROM is the ability to generate five Compatible with all popular CPUs different output frequencies, allowing one chip to work Duty cycle of 45/55 in different speed processor systems. Custom frequencies available The device also has a power-down mode that turns off Operating voltage of 3.3 V to 5.5 V the clock outputs when both select pins are low. In this Power-down mode turns off chip mode, the internal PLL is not running. 25 mA drive capability at TTL levels Advanced, low-power CMOS process Block Diagram VDD 2 PLL Clock S1:0 Synthesis CLK and Control Circuitry X1/ICLK 14.31818 MHz crystal Crystal REF Oscillator or clock input X2 GND Optional crystal capacitors IDT / ICS LOCO PLL CLOCK GENERATOR 1 ICS514 REV G 051310ICS514 LOCO PLL CLOCK GENERATOR CLOCKMULTIPLIER Pin Assignment Clock Decoding Table (MHz) with 14.31818 MHz Crystal or Clock Input X1/ICLK 8 1 X2 S1 S0 CLK Multiplier Accuracy 0 0 Power-down CLK VDD 2 7 S1 0 1 25 1.746 1 ppm GND 3 6 S0 M 0 33.33 2.328 0.008% REF 5 4 CLK M 1 40 2.794 1 ppm 1 0 50 3.492 1 ppm 8-pin (150 mil) SOIC 1 1 66.66 4.656 0.008% 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) CLK and REF stop low in power-down state Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 XI/ICLK Input Crystal connection to a 14.31818 MHz crystal or clock input. 2 VDD Power Connect to +3.3 V or +5 V. 3 GND Power Connect to ground. 4 REF Output Reference 14.31818 MHz crystal oscillator buffered clock output. 5 CLK Output Clock output per table above. 6 S0 Tri-level Input Select 0 for output clock. Connect to GND or VDD or float. See table above. 7 S1 Tri-level Input Select 1 for output clock. Connect to GND or VDD or float. See table above. 8 X2 Output Crystal connection to a 14.31818 MHz crystal. Leave unconnected for clock input. Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK outputs stops low. The crystal oscillator and REF output are still active. 2. With a clock input, the phase relationship between the input and the output clocks can change each time the device is powered on. If a fixed phase relationship is required, use the ICS571 or other zero delay multipliers. IDT / ICS LOCO PLL CLOCK GENERATOR 2 ICS514 REV G 051310