MicroClock Programmable Clock 5L2503 Generator Datasheet Description Features The 5L2503 MicroClock programmable clock generator is Configurable OE1 pin function as OE, PPS or DFC control intended for low-power, consumer, wearable and smart devices. function Proactive Power Saving (PPS) features save power during the The 5L2503 device is a 3 PLL architecture design. Each PLL is end device power down mode individually programmable, allowing up to 3 unique frequency outputs. The 5L2503 has built-in unique features such as Dynamic Frequency Control (DFC) feature allows programming Proactive Power Saving (PPS) to deliver better system level up to 4 difference frequencies switch dynamically power management. Spread spectrum clock support to lower system EMI 2 An internal OTP memory allows the user to store the configuration I C Interface in the device without programming after power-up, and then can 2 be reprogrammed again through the I C interface. Output Features The device has programmable VCO and PLL source selection 3 LVCMOS outputs: 1MHz125MHz allowing the user to do power-performance optimization based on Low Power 32.768kHz clock supported the application requirements. A low-power 32.768kHz clock is Wireless clock crystal integration and fan out directly supported with only less than 2 A current consumption for system RTC reference clock needs. Key Specifications Typical Applications 2 A operation for RTC clock 32.768kHz output SmartDevice 2.5 2.5 mm 12-DFN small form factor package Handheld Wearable applications Consumer application crystal replacements Block Diagram Power Monitor VDD1 8 OE1 POR VSS PLL1 OUT1 XOUT OSC CLKIN/ XIN Mux OUT2 PLL2 & Divider VDDO Calibration VSS PLL3 OUT3 32.768K DCO SEL DFC/ SCL DFC1/OE3 Overshoot Reduction 2 I C Engine Dynamic Frequency Control Logic (DFC) (ORT) SDA DFC0/OE2 OTP memory (1 configuration ) Proactive Power Saving Logic (PPS) 2017 Integrated Device Technology, Inc. 1 October 24, 20175L2503 Datasheet Pin Assignments Figure 1. Pin Assignments for 2.5 2.5 mm 12-DFN Top View SDA DFC0/OE2 1 12 VSS SEL DFC/SCL DFC1/OE3 2 11 OUT3 VSS 3 10 VDDO XOUT 4 9 OUT2 XIN 5 8 OE1 VDD1 8 67 OUT1 2.5 2.5 mm 12-DFN Pin Descriptions Table 1. Pin Descriptions Number Name Type Description 2 I C data pin can be DFC0 function by OTP programming or selected by 1 SDA DFC0/OE2 I/O SEL DFC at power-on default. Output enable pin for OUT2. 2 SEL DFC/SCL DFC1/ I C clock pin can be DFC1 function by OTP programming selected by 2 Input OE3 SEL DFC at power-on default. Output enable pin for OUT3. 3V Power Ground pin. SS 4 XOUT I/O Crystal oscillator interface output. 5 XIN Input Crystal oscillator interface input or clock input pin (CLKIN). 6 V Power 1.8V power rail. DD1 8 7 OUT1 Output 1.8V LVCMOS clock output. 8 OE1 Input Output enable control 1. 9 OUT2 Output 1.8V LVCMOS clock output. 10 V Power 1.8V output clock power supply pin supports OUT2/3. DDO 11 OUT3 Output 1.8V LVCMOS clock output. 12 V Power Ground pin. SS EPAD Power Connect to ground pad. 2017 Integrated Device Technology, Inc. 2 October 24, 2017