VersaClock 6E Programmable 5P49V6967 Clock Generator Datasheet Description Features The 5P49V6967 is a programmable clock generator intended for Flexible 1.8V, 2.5V, 3.3V power rails high-performance consumer, networking, industrial, computing, High-performance, low phase noise PLL, < 0.5ps RMS typical and data-communications applications. This is Renesas sixth phase jitter on outputs generation of programmable clock technology (VersaClock 6E). Four banks of internal OTP memory The frequencies are generated from a single reference clock. The In-system or factory programmable reference clock can originate from one of the two redundant clock 2 I C serial programming interface inputs. A glitchless manual switchover function allows one of the 2 0xD0 or 0xD4 I C address options allow multiple devices redundant clocks to be selected during normal operation. configured in a same system. Two select pins allow up to four different configurations to be Reference LVCMOS output clock programmed and may be used for different operating modes. Three Universal configurable outputs (OUT1, 2, 4): Differential (LVPECL, LVDS, or HCSL) Typical Applications 1kHz to 350MHz Ethernet switch/router Two single-ended (in-phase or 180 degrees out of phase) PCI Express 1.0/2.0/3.0/4.0 spread spectrum on 1kHz to 200MHz PCI Express 1.0/2.0/3.0/4.0/5.0 spread spectrum off I/O VDDs can be mixed and matched, supporting 1.8V (LVDS and LVCMOS), 2.5V, or 3.3V Broadcast video/audio timing Independent spread spectrum on each output pair Multi-function printer Four additional LPHCSL outputs (OUT 3, 5, 6, 7) Processor and FPGA clocking 1.8V low power supply Any-frequency clock conversion 1kHz to 200MHz MSAN/DSLAM/PON Programmable output enable or power-down mode Fiber Channel, SAN Available in 5 5 mm 40-VFQFPN package Telecom line cards -40 to +85C industrial temperature operation Datacenter Block Diagram VDDO0 XIN/REF OUT0 SEL I2CB VDDO1 XOUT OUT1 FOD1 OUT1B VDDO2 OUT2 FOD2 SD/OE OTP OUT2B PLL and SEL1/SDA Control SEL0/SCL Logic OEA VDDA FOD3 OUT3, 5 VDDD OEB OUT6, 7 V 4 DDO OUT4 FOD4 OUT4B 2021 Renesas Electronics Corporation. 1 R31DS0063EU0701 July 7, 2021 5P49V6967 Datasheet Contents 1. Pin Assignments ...........................................................................................................................................................................................3 2. Pin Descriptions ............................................................................................................................................................................................3 3. Absolute Maximum Ratings ..........................................................................................................................................................................6 4. Thermal Characteristics ................................................................................................................................................................................6 5. Recommended Operating Conditions...........................................................................................................................................................6 6. Electrical Characteristics ..............................................................................................................................................................................7 7. Test Loads ..................................................................................................................................................................................................14 8. Jitter Performance Characteristics..............................................................................................................................................................15 9. PCI Express Jitter Performance and Specification .....................................................................................................................................16 10. Features and Functional Blocks .................................................................................................................................................................18 10.1 Device Startup and Power-on-Reset ................................................................................................................................................18 10.2 Internal Crystal Oscillator (XIN/REF) ...............................................................................................................................................19 10.2.1 Choosing Crystals .............................................................................................................................................................19 10.2.2 Tuning the Crystal Load Capacitor ....................................................................................................................................19 10.3 Programmable Loop Filter................................................................................................................................................................21 10.4 Fractional Output Dividers (FOD) .....................................................................................................................................................21 10.4.1 Individual Spread Spectrum Modulation ...........................................................................................................................21 10.4.2 Bypass Mode ....................................................................................................................................................................21 10.4.3 Cascaded Mode ................................................................................................................................................................21 10.4.4 Dividers Alignment ............................................................................................................................................................21 10.4.5 Programmable Skew .........................................................................................................................................................22 10.5 Output Drivers ..................................................................................................................................................................................22 10.6 SD/OE Pin Function .........................................................................................................................................................................22 2 10.7 I C Operation ...................................................................................................................................................................................23 11. Typical Application Circuit ..........................................................................................................................................................................24 11.1 Input Driving the XIN/REF .............................................................................................................................................................25 11.1.1 Driving XIN/REF with a CMOS Driver ...............................................................................................................................25 11.1.2 Driving XIN with a LVPECL Driver ....................................................................................................................................26 11.2 Output Single-ended or Differential Clock Terminations ...............................................................................................................27 11.2.1 LVDS Termination .............................................................................................................................................................27 11.2.2 LVPECL Termination ........................................................................................................................................................28 11.2.3 HCSL Termination.............................................................................................................................................................29 11.2.4 LVCMOS Termination .......................................................................................................................................................29 12. Package Outline Drawings .........................................................................................................................................................................30 13. Marking Diagram .........................................................................................................................................................................................30 14. Ordering Information ...................................................................................................................................................................................30 15. Revision History ..........................................................................................................................................................................................31 2021 Renesas Electronics Corporation. 2 R31DS0063EU0701 July 7, 2021