DATASHEET EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR IDT5V19EE901 Description Features The IDT5V19EE901 is a programmable clock generator Four internal PLLs intended for high performance data-communications, Internal non-volatile EEPROM telecommunications, consumer, and networking 2 Fast (400kHz) mode I C serial interface applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related Input frequency range: 1 MHz to 200 MHz frequencies. The frequencies are generated from a single Output frequency range: 4.9 kHz to 500 MHz reference clock. The reference clock can come from one of Reference crystal input with programmable linear load the two redundant clock inputs. Automatic or manual capacitance switchover function allows any one of the redundant clocks to be selected during normal operation. Crystal frequency range: 8 MHz to 50 MHz (maximum crystal range is best effort) The IDT5V19EE901 is in-system, programmable and can 2 be programmed through the use of I C interface. An Integrated VCXO internal EEPROM allows the user to save and restore the Each PLL has a 7-bit reference divider and a 12-bit configuration of the device without having to reprogram it on feedback-divider power-up. 8-bit output-divider blocks Each of the four PLLs has an 7-bit reference divider and a Fractional division capability on one PLL 12-bit feedback divider. This allows the user to generate Two of the PLLs support spread spectrum generation four unique non-integer-related frequencies. The PLL loop capability bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can I/O Standards: tune the PLL parameters to minimize jitter generation or to Outputs - 3.3 V LVTTL/ LVCMOS maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. Outputs - LVPECL, LVDS and HCSL There are a total of six 8-bit output dividers. Each output Inputs - 3.3 V LVTTL/ LVCMOS bank can be configured to support LVTTL, LVPECL, LVDS Programmable slew rate control or HCSL logic levels. Out0 (Output 0) supports 3.3V single Programmable loop bandwidth ended output only. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to Programmable output inversion to reduce bimodal jitter route the PLL outputs to any output bank. This feature can Redundant clock inputs with auto and manual switchover be used to simplify and optimize the board layout. In options addition, each output s slew rate and enable/disable Individual output enable/disable function is programmable. Power-down mode 3.3V core V DD Available in TSSOP and VFQFPN packages -40 to +85 C Industrial Temp operation IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR 1 IDT5V19EE901 REV R 092412IDT5V19EE901 EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR CLOCK SYNTHESIZER Functional Block Diagram S R OUT0 C XIN/REF 0 XOUT S S1 PLL0 (SS) R /DIV1 C OUT1 VCXO 1 VIN controlled Logic S CLKIN R PLL1 /DIV2 OUT2 C 2 CLKSEL S OUT4 R PLL2 /DIV4 C OUT4 4 S S3 R /DIV3 C PLL3 (SS) OUT3 3 S R /DIV6 OUT6 SD/OE C 6 SDA Control S OUT5 Logic SCL R /DIV5 C OUT5 5 SEL 2:0 1. OUT1 & OUT2, OUT4 & OUT4, OUT3 & OUT6, and OUT5 & OUT5 pairs can be configured to be LVDS, LVPECL or HCSL, or two single-ended LVTTL outputs. 2. CLKIN, CLKSEL, SD/OE and SEL 2:0 have pull down resistors. IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR 2 IDT5V19EE901 REV R 092412