DATASHEET LOW PHASE NOISE CLOCK MULTIPLIER ICS601-02 Description Features The ICS601-02 is a low cost, low phase noise, high Packaged in 16-pin SOIC (Pb free) performance clock synthesizer for any application that Uses fundamental 10 - 27 MHz crystal or clock requires low phase noise and low jitter. The ICS601 is IDTs Patented PLL with the lowest phase noise lowest phase noise multiplier. Using IDTs patented analog and digital Phase Locked Loop (PLL) techniques, the chip Output clocks up to 170 MHz at 3.3 V accepts a 1027 MHz crystal or clock input, and produces Output Enable function tri-states outptus output clocks up to 170 MHz at 3.3 V. A separate supply pin Low phase noise: -132 dBc/Hz at 10 kHz is provided so that the output can be 2.5 V. Low jitter - 18 ps one sigma This product is intended for clock generation. It has low Full swing CMOS outputs with 25 mA drive capability at output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For TTL levels applications which require defined input to output timing, Advanced, low power, sub-micron CMOS process use the ICS670-01. Industrial temperature range (-40 to +85C) 3.3 V or 5 V core VDD. Output clock can operate down to 2.5 V Block Diagram VDDP VDD Reference Phase Charge Loop VCO CLK Divider Comparator Pump Filter X1/ICLK VCO Crystal Crystal or Divide Oscillator clock input X2 Optional crystal ROM Based capacitors needed Multipliers for accurate tuning (not shown) 4 OE S3:0 GND IDT LOW PHASE NOISE CLOCK MULTIPLIER 1 ICS601-02 REV G 051310ICS601-02 LOW PHASE NOISE CLOCK MULTIPLIER SYNTHESIZERS Pin Assignment Multiplier Select Table S3 S2 S1 S0 CLK CLK 1 GND 16 00 0 0 Input x4/3 VDDP 2 15 GND 00 01 Input x4 00 1 0 Input x25/4 VDD 3 14 GND 00 11 Input x3 VDD 4 13 GND 01 0 0 Input x7.5 VDD 5 12 OE 01 01 Input x5 X2 6 S0 11 01 10 Input x6 S1 7 10 S3 01 11 Input x8 X1/ICLK 8 9 S2 10 0 0 Input x8/3 10 01 Input x8 16-pin SOIC 10 1 0 Input x12.5 10 11 Input x6 11 0 0 Input x15 11 0 1 Input x10 11 1 0 Input x12 11 1 1 Input x16 0 = connect directly to ground 1 = connect directly to VDD Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 CLK Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 2 VDDP Power Supply pin for CLK output buffer. Sets output clock amplitude. Connect to 2.5V or 3.3V. 3 VDD Power Connect to +3.3V or +5V. Must match other VDDs. 4 VDD Power Connect to +3.3V or +5V. Must match other VDDs. 5 VDD Power Connect to +3.3V or +5V. Must match other VDDs. 6 X2 XO Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal. 7 S1 Input Multiplier select pin 1. Determines CLK output per table above. Internal pull-up. 8 X1/ICLK XI Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock. 9 S2 Input Multiplier select pin 2. Determines CLK output per table above. Internal pull-up. 10 S3 Input Multiplier select pin 3. Determines CLK output per table above. Internal pull-up. 11 S0 Input Multiplier select pin 0. Determines CLK output per table above. Internal pull-up. 12 OE Input Output Enable. Tri-states the output clock when low. Internal pull-up. 13 GND Power Connect to ground. 14 GND Power Connect to ground. 15 GND Power Connect to ground. 16 GND Power Connect to ground. IDT LOW PHASE NOISE CLOCK MULTIPLIER 2 ICS601-02 REV G 051310