DATASHEET NETWORKING CLOCK SOURCE ICS650-27 Description Features The ICS650-27 is a low cost, low jitter, high performance Packaged in 20-pin (150 mil) SSOP (QSOP) clock synthesizer for networking applications. Using analog Pb (lead) free package, RoHS compliant Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz fundamental crystal or clock input 12.5 MHz or 25 MHz clock or fundamental mode crystal Six output clocks with selectable frequencies input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-27 outputs SDRAM frequencies of 67, 83, 100, and 133 MHz all have zero ppm synthesis error. Buffered crystal reference output Zero ppm synthesis error in all clocks The ICS650-27 is pin compatible and functionally equivalent to the ICS650-07. It is a performance Ideal for PMC-Sierras ATM switch chips upgrade and is recommended for all new 3.3V designs. Full CMOS output swing with 25 mA output drive capability at TTL levels See the MK74CB214, ICS551, and ICS552-01 for non-PLL Advanced, low-power, sub-micron CMOS process buffer devices which produce multiple low-skew copies of these output clocks. Operating voltage of 3.3 V Industrial temperature only See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks. Block Diagram VDD 2 CLKA1 2 /2 ACS1:0 CLKA2 2 CLKB1 BCS1:0 Clock Synthesis CCS CLKB2 /2 and Control Circuitry CLKC1 CLKC2 X1/ICLK Clock Buffer/ 25 or 12.5 MHz REFOUT Crystal cyrstal or clock Oscillator X2 2 OE (all outputs) GND IDT / ICS NETWORKING CLOCK SOURCE 1 ICS650-27 REV F 051310ICS650-27 NETWORKING CLOCK SOURCE CLOCKSYNTHESIZER Pin Assignment ASC0 1 20 BCS1 X2 2 19 BCS0 X1/ICLK 3 18 REFOUT VDD 4 17 CLKA1 ASC1 5 16 VDD GND 6 15 OE CLKC1 7 14 GND CLKC2 8 13 CLKA2 CLKB2 9 12 DC CLKB1 10 11 CCS 20-pin (150 mil) SSOP Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ACS0 Input A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3. 2 X2 Input Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock input. 3 X1/ICLK Input Crystal connection. Connect to a fundamental crystal or clock input. 4 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 16. 5 ACS1 Input A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal pull-up. 6 GND Power Connect to ground. 7 CLKC1 Output Output Clock C1. Depends on setting of CCS per table on page 3. 8 CLKC2 Output Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1. 9 CLKB2 Output Output Clock B2. Depends on setting of BCS1, 0 per table on page 3. 10 CLKB1 Output Output Clock B1. Depends on setting of BCS1, 0 per table on page 3. 11 CCS Input Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3. 12 DC - Dont connect. Do not connect anything to this pin. 13 CLKA2 Output Output Clock A2. Depends on setting of ACS1, 0 per table on page 3. 14 GND Power Connect to ground. 15 OE Input Output enable. Tri-states all outputs when low. Internal pull-up. 16 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 4. 17 CLKA1 Output Output Clock A1. Depends on setting of ACS1, 0 per table on page 3. 18 REFOUT Output Buffered reference clock output. Same frequency as crystal or clock input. 19 BCS0 Input B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3. 20 BCS1 Input B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal pull-up. IDT / ICS NETWORKING CLOCK SOURCE 2 ICS650-27 REV F 051310