FemtoClock Crystal-to-LVCMOS/LVTTL ICS840021I Clock Generator DATA SHEET General Description Features The ICS840021I is a Gigabit Ethernet Clock One LVCMOS/LVTTL output, 15 output impedance ICS Generator. The ICS840021I uses a 25MHz crystal to Crystal oscillator interface designed for 25MHz, HiPerClockS synthesize 125MHz. The ICS840021I has excellent 18pF parallel resonant crystal phase jitter performance, over the 1.875MHz 20MHz Output frequency: 125MHz integration range. The ICS840021I is packaged in a VCO range: 560MHz to 680MHz small 8-pin TSSOP and 16-pin VFQFN, making it ideal for use in RMS phase jitter 125MHz, using a 25MHz crystal systems with limited board space. (1.875MHz - 20MHz): 0.48ps (typical) 3.3V RMS phase noise at 125MHz (typical) Phase noise: Offset Noise Power 100Hz ................-97.8 dBc/Hz 1kHz ..............-124.6 dBc/Hz 10kHz ..............-132.5 dBc/Hz 100Hz ..............-131.1 dBc/Hz Voltage Supply Modes: Pin Assignments V /V = 3.3V DD DDA V /V = 2.5V DD DDA VDDA VDD -40C to 85C ambient operating temperature 1 8 OE Q0 2 7 Available in both standard (RoHS 5) and lead-free (RoHS 6) XTAL OUT GND 3 6 packages XTAL IN RESERVED 4 5 ICS840021I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Block Diagram Top View Pullup OE 25MHz XTAL IN Phase Q0 OSC VCO 5 Detector 16 15 14 13 XTAL OUT 1 OE 12 Q0 XTAL OUT 2 11 VDD 25 XTAL IN 3 10 GND (fixed) nc 4 9 GND 5 6 7 8 ICS840021I 16-Lead VFQFN 3.0mm x 3.0mm x 0.925mm package body K Package Top View ICS840021AGI REVISION C JANUARY 27, 2010 1 2010 Integrated Device Technology, Inc. nc VDDA nc nc nc nc nc VDDICS840021I Data Sheet FEMTOCLOCK CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Table 1. Pin Descriptions Name Type Description V Power Analog supply pin. DDA Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to high-impedance OE Input Pullup state. LVCMOS/LVTTL interface levels. XTAL OUT, Input Crystal oscillator interface. XTAL IN is the input, XTAL OUT is the output. XTAL IN nc Unused No connect. RESERVED Reserved Reserved pin. GND Power Power supply ground. output impedance. Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 15 Power Core supply pin. V DD NOTE: Pullup refers to internal input resistors. See Table 1, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V = 3.465V 7 pF DD C Power Dissipation Capacitance PD = 2.625V 7 pF V DD R Input Pullup Resistor 51 k PULLUP R Output Impedance 15 OUT Function Table Table 3. Control Function Table Control Input Output OE Q0 0 High-Impedance 1Active ICS840021AGI REVISION C JANUARY 27, 2010 2 2010 Integrated Device Technology, Inc.