FemtoClock Crystal-to-HCSL ICS841664I Clock Generator DATA SHEET General Description Features The ICS841664I is an optimized sRIO clock generator and a Four differential HCSL clock outputs: configurable for sRIO member of the family of high-performance clock solutions from IDT. (125MHz or 156.25MHz) clock signals The device uses a 25MHz parallel crystal to generate 125MHz and One REF OUT LVCMOS/LVTTL clock output 156.25MHz clock signals, replacing solution requiring multiple oscillator and fanout buffer solutions. The device has excellent phase Selectable crystal oscillator interface, 25MHz, 18pF parallel jitter (<1ps RMS) suitable to clock components requiring precise and resonant crystal or LVCMOS/LVTTL single-ended reference clock low-jitter sRIO clock signals. Designed for telecom, networking and input or LVCMOS/LVTTL single-ended input industrial application, the ICS841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, Supports the following output frequencies: 125MHz or 156.25MHz switches and bridges. VCO: 625MHz Supports PLL bypass and output enable functions RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz): 0.45ps (typical) 125MHz Full 3.3V power supply mode -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment VDD 1 28 IREF REF OUT 2 27 FSEL0 XTAL IN 1 QA0 0 OSC GND 3 26 FSEL1 25MHz nQA0 QA004 25 QB XTAL OUT FemtoClock fref nQA0 5 24 nQB0 0 PLL NA VCO = 625MHz Pulldown V DDOA 6 23 V DDOB REF IN 1 QA1 7 22 GND GND nQA1 QA1 8 21 QB1 Pulldown REF SEL nQA1 9 20 nQB1 nREF OE 10 19 MR/nOE M = 25 QB0 BYPASS 11 18 V DD IREF REF IN 12 17 XTAL IN nQB0 NB REF SEL XTAL OUT 13 16 Pulldown VDDA 14 15 GND QB1 BYPASS Pulldown FSEL 0:1 nQB1 ICS841664I Pulldown MR/nOE 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm REF OUT package body G Package Pullup nREF OE Top View ICS841664AGI REVISION A JULY 15, 2013 1 2013 Integrated Device Technology, Inc. ICS841664I Data Sheet FEMTOCLOCK CRYSTAL-TO-HCSL CLOCK GENERATOR Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 18 V Power Core supply pins. DD 2 REF OUT Output LVCMOS/LVTTL reference frequency clock output. 3, 7, 15, 22 GND Power Power supply ground. 4, 5, QA0, nQA0 Output Differential Bank A output pairs. HCSL interface levels. 8, 9 QA1, nQA1 6V Power Output supply pin for Bank A outputs. DDOA Active low REF OUT enable/disable. See Table 3E. 10 nREF OE Input Pullup LVCMOS/LVTTL interface levels. 11 BYPASS Input Pulldown Selects PLL/PLL bypass mode. See Table 3C. LVCMOS/LVTTL interface levels. 12 REF IN Input Pulldown LVCMOS/LVTTL reference clock input. Reference select, Selects the input reference source. See Table 3B. 13 REF SEL Input Pulldown LVCMOS/LVTTL interface levels 14 V Power Analog supply pin. DDA 16, XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, Input 17 XTAL IN XTAL IN is the input. Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in high impedance. When logic 19 MR/nOE Input Pulldown LOW, the internal dividers and the outputs are enabled. See Table 3D. LVCMOS/LVTTL interface levels. 20, 21, nQB1, QB1 Output Differential Bank B output pairs. HCSL interface levels. 24, 25 nQB0, QB0 23 V Power Output supply pin for Bank B outputs. DDOB 26, FSEL1, Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels. 27 FSEL0 HCSL current reference resistor output. A fixed precision resistor (475) form this 28 IREF Output pin to ground provides a reference current used for differential current-mode QX 0:1 , nQX 0:1 clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN C Power Dissipation Capacitance V = 3.465V 4 pF PD DD R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance REF OUT V = 3.465V 20 OUT DD ICS841664AGI REVISION A JULY 15, 2013 2 2013 Integrated Device Technology, Inc.