Clock Generator for Cavium Processors ICS8430S07I DATA SHEET General Description Features The ICS8430S07I is a PLL-based clock generator One selectable differential LVPECL output pair for DDR ICS 533/400/667 specifically designed for Cavium Networks SoC HiPerClockS processors. This high performance device is optimized Six LVCMOS/ LVTTL outputs, 15 typical output impedance - One selectable core clock for the processor to generate the processor core reference clock, the - One selectable clock for the PCI/ PCI-X bus DDR reference clocks, the PCI/PCI-X bus clocks, and - One 125MHz clock reference for GbE MAC the clocks for both the Gigabit Ethernet MAC and PHY. The clock - Three 25MHz clock references for GbE PHY generator offers ultra low-jitter, low-skew clock outputs, and edge Selectable external crystal or differential (single-ended) input rates that easily meet the input requirements for the source CN3005/CN3010/CN3020 processors. The output frequencies are Crystal oscillator interface designed for 25MHz, parallel resonant generated from a 25MHz external input source or an external 25MHz crystal parallel resonant crystal. The extended temperature range of the Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, ICS8430S07I supports telecommunication, networking, and storage LVHSTL, SSTL, HCSL input levels requirements. Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels RMS phase jitter 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.78ps (typical), QD output Output supply: Applications LVPECL 3.3V Core LVCMOS Core/Output 3.3V/3.3V Systems using CN30XX MIPS64 Broadband Processors 3.3V/2.5V Networking, control and storage equipment, including routers, -40C to 85C ambient operating temperature switches, application-aware gateways, triple-play gateways, WLAN and 3G/4G access and aggregation devices, storage Available in lead-free (RoHS 6) package arrays, storage networking equipment, servers, and intelligent NICs 802.11 a/b/g/n wireless for home data and multi-media distribution QoS for high quality Voice, Video, and Data Service Next-generation PON, VDSL2, and Cable Networks High-performance NAS Pin Assignment Audio/Video Storage and Distribution Consumer Space Media Server 32 31 30 29 28 27 26 25 1 V V 24 DDO C DD 2 23 QC nPLL SEL ICS8430S07I 3 CORE SEL XTAL IN 22 32-Lead VFQFN 5mm x 5mm x 0.925mm 4 GND XTAL OUT 21 package body nXTAL SEL 5 20 GND K Package 6 CLK 19 MR/ nOE REF Top View 7 nCLK 18 QB GND 8 17 V DDO B 13 14 15 16 910 11 12 ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 1 2009 Integrated Device Technology, Inc. V PCI SEL1 DDO REF QREF0 PCI SEL0 DDR SEL1 QREF1 QREF2 DDR SEL0 V nQA DDO REF G QA ND V DD QD V V DDA DDO DICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Block Diagram PD nPLL SEL 00 = 133.333MHz DDR533, DDR400, or QA 01 = 100.000MHz DDR667 Reference PD nXTAL SEL nQA 10 = 83.333MHz Clock (LVPECL) 11 = 125.000MHz XTAL IN 0 = 50.000MHz QB Processor Core Clock OSC 25MHz 1 = 33.333MHz 0 (LVCMOS) PLL XTAL OUT 0 1 00 = 133.333MHz 01 = 100.000MHz 1 QC PCI or PCI-X Clock PD CLK 10 = 66.667MHz 25MHz (LVCMOS) PU/PD nCLK 11 = 33.333MHz QD Gigabit Ethernet MAC 125MHz GbE CLK Clock (LVCMOS) PD DDR SEL1:0 QREF0 PD CORE SEL Clock Output Gigabit Ethernet Control Logic QREF1 25MHz GbE CLK / PHY Clocks PD / (LVCMOS) PCI SEL1:0 QREF2 PD MR/nOE REF ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 2 2009 Integrated Device Technology, Inc.