Clock Generator for Cavium 8430S10I-02 Processors Data Sheet General Description Features The 8430S10I-02 is a PLL-based clock generator specifically One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core Nine LVCMOS/ LVTTL outputs, 20 typical output impedance reference clock, the DDR reference clocks, the PCI/PCI-X bus Selectable external crystal or differential (single-ended) input clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. source The clock generator offers ultra low-jitter, low-skew clock outputs, Crystal oscillator interface designed for 25MHz, parallel resonant and edge rates that easily meet the input requirements for the crystal CN30XX/CN31XX/CN38XX/CN58XX processors. The output Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, SSTL frequencies are generated from a 25MHz external input source or an input levels external 25MHz parallel resonant crystal. The extended temperature Internal resistor bias on nCLK pin allows the user to drive CLK range of the 8430S10I-02 supports telecommunication, networking, input with external single-ended (LVCMOS/ LVTTL) input levels and storage requirements. Power output supply modes LVDS and LVPECL full 3.3V LVCMOS full 3.3V or mixed 3.3V core/2.5V output -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Applications Systems using Cavium Processors CPE Gateway Design Home Media Servers 802.11n AP or Gateway Soho Secure Gateway Pin Assignment Soho SME Gateway Wireless Soho and SME VPN Solutions Wired and Wireless Network Security Web Servers and Exchange Servers 48 47 46 45 44 43 42 41 40 39 38 37 V DD 1 V 36 DDO CD 2 QC nOE D 35 GND 3 QD0 34 nPLL SEL 4 QD 33 1 ICS8430S10I-02 48- Pin TQFP, E- Pad CORE SEL XTAL IN 5 32 7mm x7mm x 7m x 7mm 1mmx 1mm XTAL OUT 6 GND 31 package body nXTAL SEL GND 7 package body 30 & Package CLK 8 29 nOE REF Y Package Top View nCLK 9 28 V DDO B Top View nOE C 10 27 QB0 nOE B QB1 11 26 GND 12 25 V DDO B 13 14 15 16 17 18 19 20 21 22 23 24 2016 Integrated Device Technology, Inc. 1 October 4, 2016 V V DD DDO REF nOE E nOE A SPI SEL1 GND SPI SEL0 QREF0 PCI SEL1 QREF1 PCI SEL0 QREF2 GND DDR SEL1 DDR SEL0 V DDO REF nQA nLVDS SEL QA GND V QE DD V DDA V DDO E8430S10I-02 Data Sheet Block Diagram nLVDS SEL 2016 Integrated Device Technology, Inc. 2 October 4, 2016