FemtoClock Crystal-to-LVDS ICS844004I-01 Frequency Synthesizer NRND NRND Not Recommend for New Designs DATA SHEET General Description Features The ICS844004I-01 is a 4 output LVDS Synthesizer optimized to Four LVDS output pairs generate Ethernet reference clock frequencies. Using a 25MHz Selectable crystal oscillator interface or LVCMOS/LVTTL 18pF parallel resonant crystal, the following frequencies can be single-ended input generated based on the 2 frequency select pins (F SEL 1:0 ): Supports the following output frequencies: 156.25MHz, 125MHz, 156.25MHz, 125MHz and 62.5MHz. The ICS844004I-01 uses IDTs 62.5MHz rd 3 generation low phase noise VCO technology and can achieve VCO range: 560MHz - 680MHz <1ps typical rms phase jitter, easily meeting Ethernet jitter RMS phase jitter 156.25MHz, using a 25MHz crystal requirements. The ICS844004I-01 is packaged in a small 24-pin (1.875MHz - 20MHz): 0.41ps (typical) TSSOP package. Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Not Recommended For New Designs Frequency Select Function Table Inputs Output Frequency (MHz), F SEL1 F SEL0 M Div. Value N Div. Value M/N Div. Value (25MHz Ref.) 0 0 25 4 6.25 156.25 (default) 0 1 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 not used not used Block Diagram Pin Assignment nQ1 1 24 nQ2 Pulldown 2 Q1 2 23 Q2 F SEL 1:0 VDDO 3 22 VDDO Pulldown nPLL SEL Q0 Q0 4 21 Q3 nQ0 5 20 nQ3 F SEL 1:0 nQ0 MR 6 19 GND Pulldown 0 0 4 (default) REF CLK 11 1 nPLL SEL 7 18 nc 0 1 5 Q1 nc 8 17 nXTAL SEL 1 0 10 25MHz VCO VDDA 9 16 REF CLK XTAL IN nQ1 1 1 not used Phase 625MHz F SEL0 10 15 GND 0 OSC 0 Detector (w/25MHz VDD 14 XTAL IN 11 Reference) XTAL OUT 12 13 F SEL1 XTAL OUT Q2 Pulldown nXTAL SEL ICS844004I-01 nQ2 24-Lead TSSOP M = 25 (fixed) 4.4mm x 7.8mm x 0.92mm Q3 package body nQ3 G Package Pulldown MR Top View ICS844004BGI-01 REVISION A MAY 20, 2013 1 2013 Integrated Device Technology, Inc.ICS844004I-01 Data Sheet FEMTOCLOCK CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number Name Type Description 1, 2 nQ1, Q1 Output Differential output pair. LVDS interface levels. 3, 22 V Power Output supply pins. DDO 4, 5 Q0, nQ0 Output Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 6 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL select. Selects between the PLL and REF CLK as input to the dividers. 7 nPLL SEL Input Pulldown When LOW, selects PLL (PLL enabled). When HIGH, the PLL is bypassed. LVCMOS/LVTTL interface levels. 8, 18 nc Unused No connect. 9V Power Analog supply pin. DDA 10, F SEL0, Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 12 F SEL1 11 V Power Core supply pin. DD 13, XTAL OUT, Input Parallel resonant crystal interface. XTAL OUT is the output, XTAL IN is the input. 14 XTAL IN 15, 19 GND Power Power supply ground. 16 REF CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF CLK inputs as the PLL reference source. 17 nXTAL SEL Input Pulldown Selects XTAL inputs when LOW. Selects REF CLK when HIGH. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVDS interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVDS interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pulldown Resistor 51 k PULLDOWN ICS844004BGI-01 REVISION A MAY 20, 2013 2 2013 Integrated Device Technology, Inc.