Two-Channel Universal Frequency 8A34045 Datasheet Translator 12 Differential / 24 LVCMOS outputs Overview Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) The 8A34045 Two-Channel Universal Frequency Translator is a Jitter below 150fs RMS (10kHz to 20MHz) highly integrated timing device with two Digital PLL (DPLL) LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL channels and six Digitally Controlled Oscillator (DCO) channels. The DPLLs can lock to external references or operate in free run, output modes supported and can also be configured as DCOs. Each DCO can be Differential output swing is selectable: 400mV / 650mV / synchronized by any of the DPLLs or they can operate in free run. 800mV / 910mV The DCOs can alternatively be controlled by an external algorithm Independent output voltages of 3.3V, 2.5V, or 1.8V for Optical Transport Network (OTN) applications. LVCMOS additionally supports 1.5V or 1.2V The clock phase of each output is individually programmable Typical Applications in 1ns to 2ns steps with a total range of 180 Core and access IP switches / routers 2 differential / 4 single-ended clock inputs Synchronous Ethernet equipment Support frequencies from 1kHz to 1GHz 10Gb, 40Gb, and 100Gb Ethernet interfaces Any input can be mapped to any or all of the timing channels Wireless infrastructure for 4.5G and 5G network equipment Redundant inputs frequency independent of each other OTN Muxponders and line cards Any input can be designated as external frame/sync pulse of EPPS (even pulse per second), 1 PPS (Pulse per Second), 5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz Features associated with a selectable reference clock input Close-in phase noise complies with Common Public Radio Per-input programmable phase offset of up to 1.638 s in Interface (CPRI) frequency synchronization requirements 50ps steps Supports all ITU-T G.709 frequencies Reference monitors qualify/disqualify references depending on Meets OTN jitter and wander requirements per ITU-T G.8251 LOS, activity, frequency monitoring, and/or LOS input pins Two independent DPLL/DCO channels Loss of Signal (LOS) input pins (via GPIOs) can be assigned Each can act as a frequency synthesizer, jitter attenuator, to any input clock reference Digitally Controlled Oscillator (DCO), or Digital Phase Lock Automatic reference selection state machines select the active Loop (DPLL) reference for each DPLL based on the reference monitors, DPLL Digital Loop Filters (DLFs) are programmable with priority tables, revertive / non-revertive, and other cut-off frequencies from 1.1Hz to 22kHz programmable settings Generate output frequencies that are independent of input System APLL operates from fundamental-mode crystal: frequencies via a Fractional Output Divider (FOD) 25MHz to 54MHz or from a crystal oscillator Each FOD supports output phase tuning with 50ps System DPLL accepts an XO, TCXO, or OCXO operating at resolution virtually any frequency from 1MHz to 150MHz Six independent DCO channels DPLLs can be configured as DCOs to synthesize clocks under the control of an external algorithm Each DCO can act as an independent DCO or as a Satellite Channel DCOs generate with frequency resolution less than -16 1.11 10 Satellite Channels are associated with a source DPLL or 2 DCO to increase the number of independently Supports a 1MHz I C or 50MHz SPI serial processor port programmable FODs and output stages available to the Can configure itself automatically after reset via: source channel Internal customer definable One-Time Programmable (OTP) Each DCO generates an independent output frequency via a memory with up to 16 different configurations Fractional Output Divider (FOD) 2 2 Standard external I C EEPROM if serial port in I C mode 1149.1 JTAG Boundary Scan 10 10 mm 72-QFN package 2020 Renesas Electronics Corporation 1 September 25, 20208A34045 Datasheet Block Diagram Figure 1. Block Diagram XO DPLL (Optional) OSCI OSCO To FODs System Osc FOD DPLL System APLL Combo Bus Div Out Q0 DPLL / FOD Reference DCO 0 Div Out Q1 Monitors CLK0 Div Out Q2 Reference DPLL / FOD Switching DCO 1 CLK1 Div Out Q3 State Machines Div Out Q4 DCO 2 FOD Div Out Q5 Div Out Q6 DCO 3 FOD Div Out Q7 DCO 4 FOD Div Out Q8 DCO 5 FOD Div Out Q9 DCO 6 FOD Div Out Q10 DCO 7 FOD Div Out Q11 Status and Configuration OTP Registers 2 2 I C Master SPI/I C GPIO / JTAG Description The 8A34045 Two-Channel Universal Frequency Translator is a highly integrated timing device with two Digital PLL (DPLL) channels, DPLL/DCO 0..1 and six Digitally Controlled Oscillator (DCO) channels, DCO 2..7 . The DPLLs can lock to external references or operate in free run, or can be configured as DCOs. Each of the DCOs can be synchronized by any of the DPLLs or another DCO, or they can operate in free run. The DCOs can alternatively be controlled by an external algorithm. The 8A34045 supports precise control of input-to-input, input-to-output, and output-to-output phase skew. The device outputs low-jitter clocks that can directly synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces, as well as SONET/SDH and PDH interfaces. 2020 Renesas Electronics Corporation 2 September 25, 2020