ICS853S031I Low Skew, 1-to-9, Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer DATA SHEET General Description Features The ICS853S031I is a low skew, high performance 1-to-9 Nine differential 2.5V, 3.3V LVPECL/ECL outputs Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The Selectable differential CLK, nCLK or LVPECL clock inputs ICS853S031I has two selectable clock inputs. The CLK, nCLK pair CLK, nCLK pair can accept the following differential input levels: can accept most standard differential input levels. The PCLK, nPCLK LVPECL, LVDS, LVHSTL, HCSL, SSTL pair can accept LVPECL, LVDS, CML or SSTL input levels. The clock PCLK, nPCLK supports the following input types: LVPECL, LVDS, enable is internally synchronized to eliminate runt pulses on the CML, SSTL outputs during asynchronous assertion/deassertion of the clock Output frequency: 1.6GHz (maximum) enable pin. Translates any single-ended input signal (LVCMOS, LVTTL, GTL) Guaranteed output and part-to-part skew characteristics make the to 3.3V LVPECL levels with resistor bias on nCLK or nPCLK ICS853S031I ideal for high performance workstation and server inputs applications. Output skew: 20ps (typical) Part-to-part skew: 90ps (typical) Propagation delay: 885ps (typical), PCLK LVPECL mode operating voltage supply range: V = 2.375V to 3.465V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.465V to -2.375V CC EE -40C to 85C ambient operating temperature Block Diagram Available lead-free (RoHS 6) package Pullup CLK EN D Q Pin Assignment LE Pulldown CLK 0 Pullup Q0 nCLK nQ0 Pulldown PCLK 1 Pullup 32 31 30 29 28 27 26 25 nPCLK Q1 VCC 1 24 VCCO nQ1 Pulldown CLK SEL CLK 2 23 Q3 Q2 nCLK 3 22 nQ3 nQ2 Q4 CLK SEL 4 21 Q3 PCLK 5 nQ4 20 nQ3 nPCLK 6 Q5 19 Q4 VEE 7 nQ5 18 nQ4 CLK EN 8 VCCO 17 9 10 11 12 13 14 15 16 Q5 nQ5 Q6 ICS853S031I nQ6 32-Lead LQFP Q7 7mm x 7mm x 1.4mm package body nQ7 Y Package Q8 Top View nQ8 ICS853S031BYI REVISION A AUGUST 17, 2011 1 2011 Integrated Device Technology, Inc. VCCO VCCO nQ8 Q0 Q8 nQ0 nQ7 Q1 Q7 nQ1 nQ6 Q2 Q6 nQ2 VCCO VCCOICS853S031I Data Sheet LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1V Power Positive supply pin. CC 2 CLK Input Pulldown Non-inverting differential clock input. 3 nCLK Input Pullup Inverting differential clock input. Clock select input. When HIGH, selects PCLK/nPCLK inputs. When LOW, selects 4 CLK SEL Input Pulldown CLK/nCLK inputs. LVTTL / LVCMOS interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 6 nPCLK Input Pullup Inverting differential LVPECL clock input. 7V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. When 8 CLK EN Input Pullup LOW, Qx outputs are forced low, nQx outputs are forced high. LVTTL/LVCMOS interface levels. 9, 16, 17, V Power Output supply pins. CCO 24, 25, 32 10, 11 Output Differential output pair. LVPECL/ECL interface levels. nQ8, Q8 12, 13 Output Differential output pair. LVPECL/ECL interface levels. nQ7, Q7 14, 15 Output Differential output pair. LVPECL/ECL interface levels. nQ6, Q6 18, 19 Output Differential output pair. LVPECL/ECL interface levels. nQ5, Q5 20, 21 Output Differential output pair. LVPECL/ECL interface levels. nQ4, Q4 22, 23 Output Differential output pair. LVPECL/ECL interface levels. nQ3, Q3 26, 27 Output Differential output pair. LVPECL/ECL interface levels. nQ2, Q2 28, 29 Output Differential output pair. LVPECL/ECL interface levels. nQ1, Q1 30, 31 Output Differential output pair. LVPECL/ECL interface levels. nQ0, Q0 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 50 k PULLDOWN R Input Pullup Resistor 50 k PULLUP ICS853S031BYI REVISION A AUGUST 17, 2011 2 2011 Integrated Device Technology, Inc.